Initial commit
This commit is contained in:
@@ -0,0 +1,78 @@
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#pragma once
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#include <stdint.h>
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static inline uint64_t asm_rdmsr(uint32_t msr) {
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uint32_t eax;
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uint32_t edx;
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asm volatile("rdmsr" : "=a"(eax), "=d"(edx) : "c"(msr) : "memory");
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return ((uint64_t)edx << 32) | eax;
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}
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// Writes a 64-bit value to a given MSR.
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static inline void asm_wrmsr(uint32_t msr, uint64_t val) {
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uint32_t eax = (uint32_t)val;
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uint32_t edx = val >> 32;
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asm volatile("wrmsr" : : "a"(eax), "d"(edx), "c"(msr) : "memory");
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}
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// Writes a 64-bit value to a control register using XSETBV.
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static inline void asm_wrxcr(uint32_t reg, uint64_t val) {
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uint32_t eax = val;
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uint32_t edx = val >> 32;
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asm volatile("xsetbv" ::"a"(eax), "d"(edx), "c"(reg) : "memory");
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}
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// Saves the FPU state to a 512-byte region of memory using FXSAVE.
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// Pointer must be 16-byte aligned.
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static inline void asm_fxsave(void* mem) {
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asm volatile("fxsave %0" : "+m"(*(uint8_t*)mem)::"memory");
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}
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// Restores the FPU state from a 512-byte region of memory using FXRSTOR.
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// Pointer must be 16-byte aligned.
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static inline void asm_fxrstor(void* mem) {
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asm volatile("fxrstor %0" ::"m"(*(uint8_t*)mem) : "memory");
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}
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// Saves the FPU state to a region of memory using XSAVE.
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// Pointer must be 16-byte aligned.
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static inline void asm_xsave(void* mem) {
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asm volatile("xsave %0" : "+m"(*(uint8_t*)mem)::"memory");
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}
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// Restores the FPU state from a region of memory using XRSTOR.
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// Pointer must be 16-byte aligned.
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static inline void asm_xrstor(void* mem) {
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asm volatile("xrstor %0" ::"m"(*(uint8_t*)mem) : "memory");
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}
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static inline uint8_t asm_inb(uint16_t port) {
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uint8_t result;
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asm volatile("in %0, %1" : "=a"(result) : "Nd"(port));
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return result;
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}
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static inline uint16_t asm_inw(uint16_t port) {
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uint16_t result;
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asm volatile("in %0, %1" : "=a"(result) : "Nd"(port));
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return result;
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}
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static inline uint32_t asm_inl(uint16_t port) {
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uint32_t result;
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asm volatile("in %0, %1" : "=a"(result) : "Nd"(port));
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return result;
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}
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static inline void asm_outb(uint16_t port, uint8_t value) {
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asm volatile("out %0, %1" : : "Nd"(port), "a"(value));
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}
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static inline void asm_outw(uint16_t port, uint16_t value) {
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asm volatile("out %0, %1" : : "Nd"(port), "a"(value));
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}
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static inline void asm_outl(uint16_t port, uint32_t value) {
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asm volatile("out %0, %1" : : "Nd"(port), "a"(value));
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}
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@@ -0,0 +1,13 @@
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#pragma once
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#define ELF_ARCH_CLASS ELFCLASS64
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#define ELF_ARCH_DATA ELFDATA2LSB
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#define ELF_ARCH_MACHINE EM_X86_64
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#define elf_hdr elf64_hdr
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#define elf_phdr elf64_phdr
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#define elf_dyn elf64_dyn
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#define elf_addr elf64_addr
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#define elf_off elf64_off
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#define elf_nhdr elf64_nhdr
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#define elf_auxv elf64_auxv
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@@ -0,0 +1,17 @@
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#pragma once
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#include <defs.h>
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#include <stdint.h>
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static inline bool arch_irq_get_state() {
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uint64_t flags;
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asm volatile("pushf; pop %0" : "=r"(flags)::"memory");
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return flags & RFLAGS_IF;
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}
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static inline void arch_irq_set_state(bool state) {
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if (state)
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asm volatile("sti");
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else
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asm volatile("cli");
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}
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@@ -0,0 +1,41 @@
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#pragma once
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#include <kernel/types.h>
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#include <stddef.h>
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#include <stdint.h>
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static inline size_t arch_mem_page_bits() {
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return 12;
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}
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static inline size_t arch_mem_level_bits() {
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return 9;
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}
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static inline size_t arch_mem_num_levels() {
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return 4;
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}
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static inline virt_t arch_mem_hhdm_addr() {
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return 0xFFFF'8000'0000'0000;
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}
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static inline virt_t arch_mem_pfndb_addr() {
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return 0xFFFF'A000'0000'0000;
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}
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static inline virt_t arch_mem_mapping_addr() {
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return 0xFFFF'C000'0000'0000;
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}
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typedef uint64_t pte_t;
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enum pte_flags;
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enum cache_mode;
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struct page_table;
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void arch_mem_pte_clear(pte_t* pte);
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pte_t arch_mem_pte_build(phys_t addr, enum pte_flags flags, enum cache_mode cache);
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bool arch_mem_pte_is_present(pte_t* pte);
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bool arch_mem_pte_is_dir(pte_t* pte);
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phys_t arch_mem_pte_address(pte_t* pte);
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void arch_mem_pt_set(struct page_table* pt);
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@@ -0,0 +1,16 @@
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#pragma once
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#include <gdt.h>
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#include <stdint.h>
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static inline struct percpu* arch_percpu_get() {
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struct percpu* result;
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asm volatile("mov %0, gs:0" : "=r"(result)::"memory");
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return result;
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}
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struct arch_percpu {
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uint32_t lapic_id;
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struct gdt gdt;
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struct tss tss;
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};
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@@ -0,0 +1,35 @@
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#pragma once
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#include <stdint.h>
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struct arch_task_context {
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uint64_t rsp;
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uint8_t* fpu_region;
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uint16_t ds, es, fs, gs;
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uint64_t fs_base, gs_base;
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};
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struct arch_context {
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uint64_t r15;
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uint64_t r14;
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uint64_t r13;
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uint64_t r12;
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uint64_t r11;
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uint64_t r10;
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uint64_t r9;
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uint64_t r8;
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uint64_t rsi;
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uint64_t rdi;
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uint64_t rbp;
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uint64_t rdx;
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uint64_t rcx;
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uint64_t rbx;
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uint64_t rax;
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uint64_t isr; // Pushed onto the stack by the interrupt handler stubs.
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uint64_t error; // Pushed onto the stack by the CPU if the interrupt has an error code.
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uint64_t rip; // The rest is pushed onto the stack by the CPU during an interrupt.
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uint64_t cs;
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uint64_t rflags;
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uint64_t rsp;
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uint64_t ss;
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};
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@@ -0,0 +1,7 @@
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#pragma once
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#include <stdint.h>
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typedef uint64_t phys_t;
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typedef uint64_t virt_t;
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typedef uint64_t reg_t;
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@@ -0,0 +1,9 @@
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#pragma once
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#include <kernel/compiler.h>
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#include <stddef.h>
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#include <stdint.h>
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bool arch_usercopy_read(uint8_t* dst, const __user uint8_t* src, size_t len);
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bool arch_usercopy_write(__user uint8_t* dst, const uint8_t* src, size_t len);
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bool arch_usercopy_strlen(const __user uint8_t* str, size_t max, size_t* len);
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@@ -0,0 +1,191 @@
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#pragma once
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#define CPUID_1C_SSE3 (1 << 0)
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#define CPUID_1C_PCLMUL (1 << 1)
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#define CPUID_1C_DTES64 (1 << 2)
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#define CPUID_1C_MONITOR (1 << 3)
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#define CPUID_1C_DS_CPL (1 << 4)
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#define CPUID_1C_VMX (1 << 5)
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#define CPUID_1C_SMX (1 << 6)
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#define CPUID_1C_EST (1 << 7)
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#define CPUID_1C_TM2 (1 << 8)
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#define CPUID_1C_SSSE3 (1 << 9)
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#define CPUID_1C_CID (1 << 10)
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#define CPUID_1C_SDBG (1 << 11)
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#define CPUID_1C_FMA (1 << 12)
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#define CPUID_1C_CX16 (1 << 13)
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#define CPUID_1C_XTPR (1 << 14)
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#define CPUID_1C_PDCM (1 << 15)
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#define CPUID_1C_PCID (1 << 17)
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#define CPUID_1C_DCA (1 << 18)
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#define CPUID_1C_SSE4_1 (1 << 19)
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#define CPUID_1C_SSE4_2 (1 << 20)
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#define CPUID_1C_X2APIC (1 << 21)
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#define CPUID_1C_MOVBE (1 << 22)
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#define CPUID_1C_POPCNT (1 << 23)
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#define CPUID_1C_TSC (1 << 24)
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#define CPUID_1C_AES (1 << 25)
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#define CPUID_1C_XSAVE (1 << 26)
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#define CPUID_1C_OSXSAVE (1 << 27)
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#define CPUID_1C_AVX (1 << 28)
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#define CPUID_1C_F16C (1 << 29)
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#define CPUID_1C_RDRAND (1 << 30)
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#define CPUID_1C_HYPERVISOR (1 << 31)
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#define CPUID_1D_FPU (1 << 0)
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#define CPUID_1D_VME (1 << 1)
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#define CPUID_1D_DE (1 << 2)
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#define CPUID_1D_PSE (1 << 3)
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#define CPUID_1D_TSC (1 << 4)
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#define CPUID_1D_MSR (1 << 5)
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#define CPUID_1D_PAE (1 << 6)
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#define CPUID_1D_MCE (1 << 7)
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#define CPUID_1D_CX8 (1 << 8)
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#define CPUID_1D_APIC (1 << 9)
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#define CPUID_1D_SEP (1 << 11)
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#define CPUID_1D_MTRR (1 << 12)
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#define CPUID_1D_PGE (1 << 13)
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#define CPUID_1D_MCA (1 << 14)
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#define CPUID_1D_CMOV (1 << 15)
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#define CPUID_1D_PAT (1 << 16)
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#define CPUID_1D_PSE36 (1 << 17)
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#define CPUID_1D_PSN (1 << 18)
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#define CPUID_1D_CLFLUSH (1 << 19)
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#define CPUID_1D_DS (1 << 21)
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#define CPUID_1D_ACPI (1 << 22)
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#define CPUID_1D_MMX (1 << 23)
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#define CPUID_1D_FXSR (1 << 24)
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#define CPUID_1D_SSE (1 << 25)
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#define CPUID_1D_SSE2 (1 << 26)
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#define CPUID_1D_SS (1 << 27)
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#define CPUID_1D_HTT (1 << 28)
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#define CPUID_1D_TM (1 << 29)
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#define CPUID_1D_IA64 (1 << 30)
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#define CPUID_1D_PBE (1 << 31)
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#define CPUID_7B_FSGSBASE (1 << 0)
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#define CPUID_7B_SGX (1 << 2)
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#define CPUID_7B_BMI (1 << 3)
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#define CPUID_7B_HLE (1 << 4)
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#define CPUID_7B_AVX2 (1 << 5)
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#define CPUID_7B_SMEP (1 << 7)
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#define CPUID_7B_BMI2 (1 << 8)
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#define CPUID_7B_RTM (1 << 11)
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#define CPUID_7B_AVX512F (1 << 16)
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#define CPUID_7B_AVX512DQ (1 << 17)
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#define CPUID_7B_RDSEED (1 << 18)
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#define CPUID_7B_ADX (1 << 19)
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#define CPUID_7B_SMAP (1 << 20)
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#define CPUID_7B_AVX512IFMA (1 << 21)
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#define CPUID_7B_CLFLUSHOPT (1 << 23)
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#define CPUID_7B_CLWB (1 << 24)
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#define CPUID_7B_AVX512CD (1 << 28)
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#define CPUID_7B_SHA (1 << 29)
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#define CPUID_7B_AVX512BW (1 << 30)
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#define CPUID_7B_AVX512VL (1 << 31)
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#define CPUID_7C_AVX512VBMI (1 << 1)
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#define CPUID_7C_UMIP (1 << 2)
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#define CPUID_7C_PKU (1 << 3)
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#define CPUID_7C_OSPKE (1 << 4)
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#define CPUID_7C_WAITPKG (1 << 5)
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#define CPUID_7C_AVX512VBMI2 (1 << 6)
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#define CPUID_7C_SHSTK (1 << 7)
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#define CPUID_7C_GFNI (1 << 8)
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#define CPUID_7C_VAES (1 << 9)
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#define CPUID_7C_VPCLMULQDQ (1 << 10)
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#define CPUID_7C_AVX512VNNI (1 << 11)
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#define CPUID_7C_AVX512BITALG (1 << 12)
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#define CPUID_7C_TME_EN (1 << 13)
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#define CPUID_7C_AVX512VPOPCNTDQ (1 << 14)
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#define CPUID_7C_RDPID (1 << 22)
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#define CPUID_7C_KL (1 << 23)
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#define CPUID_7C_CLDEMOTE (1 << 25)
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#define CPUID_7C_MOVDIRI (1 << 27)
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#define CPUID_7C_MOVDIR64B (1 << 28)
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#define CPUID_7C_ENQCMD (1 << 29)
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#define CPUID_7D_UINTR (1 << 5)
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#define CPUID_7D_AVX512VP2INTERSECT (1 << 8)
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#define CPUID_7D_SERIALIZE (1 << 14)
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#define CPUID_7D_TSXLDTRK (1 << 16)
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#define CPUID_7D_PCONFIG (1 << 18)
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#define CPUID_7D_IBT (1 << 20)
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#define CPUID_7D_AMX_BF16 (1 << 22)
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#define CPUID_7D_AVX512FP16 (1 << 23)
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#define CPUID_7D_AMX_TILE (1 << 24)
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#define CPUID_7D_AMX_INT8 (1 << 25)
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#define RFLAGS_CF (1u << 0)
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#define RFLAGS_PF (1u << 2)
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#define RFLAGS_AF (1u << 4)
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#define RFLAGS_ZF (1u << 6)
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#define RFLAGS_SF (1u << 7)
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#define RFLAGS_TF (1u << 8)
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#define RFLAGS_IF (1u << 9)
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#define RFLAGS_DF (1u << 10)
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#define RFLAGS_OF (1u << 11)
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#define RFLAGS_IOPL (3u << 12)
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#define RFLAGS_NT (1u << 14)
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#define RFLAGS_RF (1u << 16)
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#define RFLAGS_VM (1u << 17)
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#define RFLAGS_AC (1u << 18)
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#define RFLAGS_VIF (1u << 19)
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#define RFLAGS_VIP (1u << 20)
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#define RFLAGS_ID (1u << 21)
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||||
|
||||
#define CR0_PE (1 << 0)
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#define CR0_MP (1 << 1)
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#define CR0_EM (1 << 2)
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#define CR0_TS (1 << 3)
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#define CR0_ET (1 << 4)
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#define CR0_NE (1 << 5)
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#define CR0_WP (1 << 16)
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#define CR0_AM (1 << 18)
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#define CR0_NW (1 << 29)
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#define CR0_CD (1 << 30)
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#define CR0_PG (1 << 31)
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#define CR4_VME (1 << 0)
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#define CR4_PVI (1 << 1)
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#define CR4_TSD (1 << 2)
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#define CR4_DE (1 << 3)
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#define CR4_PSE (1 << 4)
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#define CR4_PAE (1 << 5)
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#define CR4_MCE (1 << 6)
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#define CR4_PGE (1 << 7)
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||||
#define CR4_PCE (1 << 8)
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#define CR4_OSFXSR (1 << 9)
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#define CR4_OSXMMEXCPT (1 << 10)
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#define CR4_UMIP (1 << 11)
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#define CR4_VMXE (1 << 13)
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#define CR4_SMXE (1 << 14)
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#define CR4_FSGSBASE (1 << 16)
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#define CR4_PCIDE (1 << 17)
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#define CR4_OSXSAVE (1 << 18)
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#define CR4_SMEP (1 << 20)
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#define CR4_SMAP (1 << 21)
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#define CR4_PKE (1 << 22)
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#define CR4_CET (1 << 23)
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#define CR4_PKS (1 << 24)
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|
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#define MSR_EFER_SCE (1 << 0)
|
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#define MSR_EFER_LME (1 << 8)
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||||
#define MSR_EFER_LMA (1 << 10)
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||||
#define MSR_EFER_NXE (1 << 11)
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||||
#define MSR_EFER_SVME (1 << 12)
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#define MSR_EFER_LMSLE (1 << 13)
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#define MSR_EFER_FFXSR (1 << 14)
|
||||
#define MSR_EFER_TCE (1 << 15)
|
||||
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#define MSR_EFER (0xC0000080)
|
||||
#define MSR_STAR (0xC0000081)
|
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#define MSR_LSTAR (0xC0000082)
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#define MSR_CSTAR (0xC0000083)
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#define MSR_SFMASK (0xC0000084)
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#define MSR_FS_BASE (0xC0000100)
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#define MSR_GS_BASE (0xC0000101)
|
||||
#define MSR_KERNEL_GS_BASE (0xC0000102)
|
||||
|
||||
#define CPL_USER (0b11)
|
||||
#define CPL_KERNEL (0b00)
|
||||
@@ -0,0 +1,28 @@
|
||||
#pragma once
|
||||
|
||||
#include <kernel/compiler.h>
|
||||
#include <stdint.h>
|
||||
#include "tss.h"
|
||||
|
||||
struct [[__packed]] gdt {
|
||||
uint64_t null;
|
||||
uint64_t kernel_code32;
|
||||
uint64_t kernel_data32;
|
||||
uint64_t kernel_code64;
|
||||
uint64_t kernel_data64;
|
||||
uint64_t user_code;
|
||||
uint64_t user_data;
|
||||
uint64_t user_code64;
|
||||
uint64_t tss[2];
|
||||
};
|
||||
|
||||
struct [[__packed]] gdtr {
|
||||
uint16_t limit;
|
||||
struct gdt* base;
|
||||
};
|
||||
|
||||
// Initializes a GDT on the local core.
|
||||
void gdt_init();
|
||||
|
||||
// Sets the Task State Segment in the given GDT.
|
||||
void gdt_set_tss(struct gdt* gdt, struct tss* tss);
|
||||
@@ -0,0 +1 @@
|
||||
#pragma once
|
||||
@@ -0,0 +1,49 @@
|
||||
#pragma once
|
||||
|
||||
#define SMP_GDTR_OFFSET 80
|
||||
#define SMP_FARJMP_OFFSET 90
|
||||
#define SMP_TEMP_STACK_OFFSET 98
|
||||
#define SMP_TEMP_CR3_OFFSET 102
|
||||
#define SMP_ENTRY_OFFSET 106
|
||||
#define SMP_HHDM_OFFSET 114
|
||||
#define SMP_KERNEL32_DS 16
|
||||
#define SMP_KERNEL64_CS 24
|
||||
#define SMP_KERNEL64_DS 32
|
||||
#define SMP_INFO_SIZE 127
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <gdt.h>
|
||||
#include <kernel/common.h>
|
||||
#include <kernel/compiler.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
struct [[__packed]] smp_info {
|
||||
struct gdt gdt;
|
||||
struct gdtr gdtr;
|
||||
uint32_t farjmp_offset;
|
||||
uint32_t farjmp_segment;
|
||||
uint32_t temp_stack;
|
||||
uint32_t temp_cr3;
|
||||
uint64_t entry;
|
||||
uint64_t hhdm_offset;
|
||||
uint32_t lapic_id;
|
||||
uint8_t booted;
|
||||
};
|
||||
|
||||
static_assert(SMP_GDTR_OFFSET == offsetof(struct smp_info, gdtr));
|
||||
static_assert(SMP_FARJMP_OFFSET == offsetof(struct smp_info, farjmp_offset));
|
||||
static_assert(SMP_TEMP_STACK_OFFSET == offsetof(struct smp_info, temp_stack));
|
||||
static_assert(SMP_TEMP_CR3_OFFSET == offsetof(struct smp_info, temp_cr3));
|
||||
static_assert(SMP_ENTRY_OFFSET == offsetof(struct smp_info, entry));
|
||||
static_assert(SMP_HHDM_OFFSET == offsetof(struct smp_info, hhdm_offset));
|
||||
static_assert(SMP_KERNEL32_DS == offsetof(struct gdt, kernel_data32));
|
||||
static_assert(SMP_KERNEL64_CS == offsetof(struct gdt, kernel_code64));
|
||||
static_assert(SMP_KERNEL64_DS == offsetof(struct gdt, kernel_data64));
|
||||
static_assert(SMP_INFO_SIZE == sizeof(struct smp_info));
|
||||
|
||||
// Initializes a LAPIC.
|
||||
void x86_64_smp_init(uint32_t id);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,24 @@
|
||||
#pragma once
|
||||
|
||||
#include <kernel/compiler.h>
|
||||
#include <stdint.h>
|
||||
|
||||
struct [[__packed, __aligned(0x10)]] tss {
|
||||
uint32_t reserved0;
|
||||
uint64_t rsp0;
|
||||
uint64_t rsp1;
|
||||
uint64_t rsp2;
|
||||
uint32_t reserved1;
|
||||
uint32_t reserved2;
|
||||
uint64_t ist1;
|
||||
uint64_t ist2;
|
||||
uint64_t ist3;
|
||||
uint64_t ist4;
|
||||
uint64_t ist5;
|
||||
uint64_t ist6;
|
||||
uint64_t ist7;
|
||||
uint32_t reserved3;
|
||||
uint32_t reserved4;
|
||||
uint16_t reserved5;
|
||||
uint16_t iopb;
|
||||
};
|
||||
Reference in New Issue
Block a user