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@@ -54,6 +54,10 @@ void lapic_init(struct local_apic* lapic) {
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asm_wrmsr(0x1B, apic_msr);
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lapic->id = lapic_read_reg(lapic, APIC_REG_ID);
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if (lapic->xapic_regs)
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lapic->id >>= 24;
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// Reset the TPR.
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lapic_write_reg(lapic, APIC_REG_TPR, 0);
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// Enable APIC bit in the SIVR.
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@@ -84,6 +88,34 @@ void lapic_eoi(struct local_apic* lapic) {
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lapic_write_reg(lapic, APIC_REG_EOI, 0);
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}
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void lapic_send_ipi(
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struct local_apic* lapic,
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uint32_t target,
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uint8_t vector,
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enum apic_delivery_mode delivery_mode,
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enum apic_dest_mode dest_mode,
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enum apic_level level,
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enum apic_trigger_mode trigger_mode
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) {
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uint64_t icr = vector;
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icr |= (uint64_t)delivery_mode << 8;
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icr |= (uint64_t)dest_mode << 11;
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icr |= (uint64_t)level << 14;
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icr |= (uint64_t)trigger_mode << 15;
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if (lapic->xapic_regs)
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icr |= (uint64_t)(uint8_t)target << 56;
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else
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icr |= (uint64_t)target << 32;
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lapic_write_reg(lapic, APIC_REG_ICR, icr);
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if (lapic->xapic_regs) {
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while (lapic_read_reg(lapic, APIC_REG_ICR) & (APIC_DELIVERY_STATUS_PENDING << 12))
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asm volatile("pause");
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}
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}
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constexpr uint16_t PIC1_COMMAND_PORT = 0x20;
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constexpr uint16_t PIC1_DATA_PORT = 0x21;
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constexpr uint16_t PIC2_COMMAND_PORT = 0xA0;
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