#pragma once #define CPUID_1C_SSE3 (1 << 0) #define CPUID_1C_PCLMUL (1 << 1) #define CPUID_1C_DTES64 (1 << 2) #define CPUID_1C_MONITOR (1 << 3) #define CPUID_1C_DS_CPL (1 << 4) #define CPUID_1C_VMX (1 << 5) #define CPUID_1C_SMX (1 << 6) #define CPUID_1C_EST (1 << 7) #define CPUID_1C_TM2 (1 << 8) #define CPUID_1C_SSSE3 (1 << 9) #define CPUID_1C_CID (1 << 10) #define CPUID_1C_SDBG (1 << 11) #define CPUID_1C_FMA (1 << 12) #define CPUID_1C_CX16 (1 << 13) #define CPUID_1C_XTPR (1 << 14) #define CPUID_1C_PDCM (1 << 15) #define CPUID_1C_PCID (1 << 17) #define CPUID_1C_DCA (1 << 18) #define CPUID_1C_SSE4_1 (1 << 19) #define CPUID_1C_SSE4_2 (1 << 20) #define CPUID_1C_X2APIC (1 << 21) #define CPUID_1C_MOVBE (1 << 22) #define CPUID_1C_POPCNT (1 << 23) #define CPUID_1C_TSC (1 << 24) #define CPUID_1C_AES (1 << 25) #define CPUID_1C_XSAVE (1 << 26) #define CPUID_1C_OSXSAVE (1 << 27) #define CPUID_1C_AVX (1 << 28) #define CPUID_1C_F16C (1 << 29) #define CPUID_1C_RDRAND (1 << 30) #define CPUID_1C_HYPERVISOR (1 << 31) #define CPUID_1D_FPU (1 << 0) #define CPUID_1D_VME (1 << 1) #define CPUID_1D_DE (1 << 2) #define CPUID_1D_PSE (1 << 3) #define CPUID_1D_TSC (1 << 4) #define CPUID_1D_MSR (1 << 5) #define CPUID_1D_PAE (1 << 6) #define CPUID_1D_MCE (1 << 7) #define CPUID_1D_CX8 (1 << 8) #define CPUID_1D_APIC (1 << 9) #define CPUID_1D_SEP (1 << 11) #define CPUID_1D_MTRR (1 << 12) #define CPUID_1D_PGE (1 << 13) #define CPUID_1D_MCA (1 << 14) #define CPUID_1D_CMOV (1 << 15) #define CPUID_1D_PAT (1 << 16) #define CPUID_1D_PSE36 (1 << 17) #define CPUID_1D_PSN (1 << 18) #define CPUID_1D_CLFLUSH (1 << 19) #define CPUID_1D_DS (1 << 21) #define CPUID_1D_ACPI (1 << 22) #define CPUID_1D_MMX (1 << 23) #define CPUID_1D_FXSR (1 << 24) #define CPUID_1D_SSE (1 << 25) #define CPUID_1D_SSE2 (1 << 26) #define CPUID_1D_SS (1 << 27) #define CPUID_1D_HTT (1 << 28) #define CPUID_1D_TM (1 << 29) #define CPUID_1D_IA64 (1 << 30) #define CPUID_1D_PBE (1 << 31) #define CPUID_7B_FSGSBASE (1 << 0) #define CPUID_7B_SGX (1 << 2) #define CPUID_7B_BMI (1 << 3) #define CPUID_7B_HLE (1 << 4) #define CPUID_7B_AVX2 (1 << 5) #define CPUID_7B_SMEP (1 << 7) #define CPUID_7B_BMI2 (1 << 8) #define CPUID_7B_RTM (1 << 11) #define CPUID_7B_AVX512F (1 << 16) #define CPUID_7B_AVX512DQ (1 << 17) #define CPUID_7B_RDSEED (1 << 18) #define CPUID_7B_ADX (1 << 19) #define CPUID_7B_SMAP (1 << 20) #define CPUID_7B_AVX512IFMA (1 << 21) #define CPUID_7B_CLFLUSHOPT (1 << 23) #define CPUID_7B_CLWB (1 << 24) #define CPUID_7B_AVX512CD (1 << 28) #define CPUID_7B_SHA (1 << 29) #define CPUID_7B_AVX512BW (1 << 30) #define CPUID_7B_AVX512VL (1 << 31) #define CPUID_7C_AVX512VBMI (1 << 1) #define CPUID_7C_UMIP (1 << 2) #define CPUID_7C_PKU (1 << 3) #define CPUID_7C_OSPKE (1 << 4) #define CPUID_7C_WAITPKG (1 << 5) #define CPUID_7C_AVX512VBMI2 (1 << 6) #define CPUID_7C_SHSTK (1 << 7) #define CPUID_7C_GFNI (1 << 8) #define CPUID_7C_VAES (1 << 9) #define CPUID_7C_VPCLMULQDQ (1 << 10) #define CPUID_7C_AVX512VNNI (1 << 11) #define CPUID_7C_AVX512BITALG (1 << 12) #define CPUID_7C_TME_EN (1 << 13) #define CPUID_7C_AVX512VPOPCNTDQ (1 << 14) #define CPUID_7C_RDPID (1 << 22) #define CPUID_7C_KL (1 << 23) #define CPUID_7C_CLDEMOTE (1 << 25) #define CPUID_7C_MOVDIRI (1 << 27) #define CPUID_7C_MOVDIR64B (1 << 28) #define CPUID_7C_ENQCMD (1 << 29) #define CPUID_7D_UINTR (1 << 5) #define CPUID_7D_AVX512VP2INTERSECT (1 << 8) #define CPUID_7D_SERIALIZE (1 << 14) #define CPUID_7D_TSXLDTRK (1 << 16) #define CPUID_7D_PCONFIG (1 << 18) #define CPUID_7D_IBT (1 << 20) #define CPUID_7D_AMX_BF16 (1 << 22) #define CPUID_7D_AVX512FP16 (1 << 23) #define CPUID_7D_AMX_TILE (1 << 24) #define CPUID_7D_AMX_INT8 (1 << 25) #define RFLAGS_CF (1u << 0) #define RFLAGS_PF (1u << 2) #define RFLAGS_AF (1u << 4) #define RFLAGS_ZF (1u << 6) #define RFLAGS_SF (1u << 7) #define RFLAGS_TF (1u << 8) #define RFLAGS_IF (1u << 9) #define RFLAGS_DF (1u << 10) #define RFLAGS_OF (1u << 11) #define RFLAGS_IOPL (3u << 12) #define RFLAGS_NT (1u << 14) #define RFLAGS_RF (1u << 16) #define RFLAGS_VM (1u << 17) #define RFLAGS_AC (1u << 18) #define RFLAGS_VIF (1u << 19) #define RFLAGS_VIP (1u << 20) #define RFLAGS_ID (1u << 21) #define CR0_PE (1 << 0) #define CR0_MP (1 << 1) #define CR0_EM (1 << 2) #define CR0_TS (1 << 3) #define CR0_ET (1 << 4) #define CR0_NE (1 << 5) #define CR0_WP (1 << 16) #define CR0_AM (1 << 18) #define CR0_NW (1 << 29) #define CR0_CD (1 << 30) #define CR0_PG (1 << 31) #define CR4_VME (1 << 0) #define CR4_PVI (1 << 1) #define CR4_TSD (1 << 2) #define CR4_DE (1 << 3) #define CR4_PSE (1 << 4) #define CR4_PAE (1 << 5) #define CR4_MCE (1 << 6) #define CR4_PGE (1 << 7) #define CR4_PCE (1 << 8) #define CR4_OSFXSR (1 << 9) #define CR4_OSXMMEXCPT (1 << 10) #define CR4_UMIP (1 << 11) #define CR4_VMXE (1 << 13) #define CR4_SMXE (1 << 14) #define CR4_FSGSBASE (1 << 16) #define CR4_PCIDE (1 << 17) #define CR4_OSXSAVE (1 << 18) #define CR4_SMEP (1 << 20) #define CR4_SMAP (1 << 21) #define CR4_PKE (1 << 22) #define CR4_CET (1 << 23) #define CR4_PKS (1 << 24) #define MSR_EFER_SCE (1 << 0) #define MSR_EFER_LME (1 << 8) #define MSR_EFER_LMA (1 << 10) #define MSR_EFER_NXE (1 << 11) #define MSR_EFER_SVME (1 << 12) #define MSR_EFER_LMSLE (1 << 13) #define MSR_EFER_FFXSR (1 << 14) #define MSR_EFER_TCE (1 << 15) #define MSR_EFER (0xC0000080) #define MSR_STAR (0xC0000081) #define MSR_LSTAR (0xC0000082) #define MSR_CSTAR (0xC0000083) #define MSR_SFMASK (0xC0000084) #define MSR_FS_BASE (0xC0000100) #define MSR_GS_BASE (0xC0000101) #define MSR_KERNEL_GS_BASE (0xC0000102) #define CPL_USER (0b11) #define CPL_KERNEL (0b00)