78 lines
2.0 KiB
C
78 lines
2.0 KiB
C
#include <zinnia/percpu.h>
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#include <stddef.h>
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#include <string.h>
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#include <x86_64/asm.h>
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#include <x86_64/defs.h>
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#include <x86_64/gdt.h>
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#include <x86_64/percpu.h>
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#include <x86_64/tss.h>
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static const struct gdt main_gdt = {
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.null = {0},
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.kernel_code32 = {.val = 0x00cf9b000000ffff},
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.kernel_data32 = {.val = 0x00cf93000000ffff},
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.kernel_code64 = {.val = 0x00a09b0000000000},
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.kernel_data64 = {.val = 0x0000930000000000},
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.user_code32 = {.val = 0x00cffb000000ffff},
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.user_data = {.val = 0x0000f30000000000},
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.user_code64 = {.val = 0x00a0fb0000000000},
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.tss = {
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.limit0 = sizeof(struct tss) - 1,
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.access = 0x89, // Present | DPL=0 | System | 64-bit TSS
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.limit1_flags = ((sizeof(struct tss) - 1) >> 16) & 0x0F,
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.reserved = 0,
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},
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};
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void gdt_load() {
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struct gdt* gdt = &percpu_ref(arch_data)->gdt;
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memcpy(gdt, &main_gdt, sizeof(main_gdt));
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struct tss* tss = &percpu_ref(arch_data)->tss;
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tss->iopb = sizeof(struct tss);
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uintptr_t tss_addr = (uintptr_t)tss;
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gdt->tss.base0 = tss_addr;
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gdt->tss.base1 = tss_addr >> 16;
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gdt->tss.base2 = tss_addr >> 24;
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gdt->tss.base3 = tss_addr >> 32;
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struct gdtr gdtr = {
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.limit = sizeof(struct gdt) - 1,
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.base = gdt,
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};
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asm volatile("lgdt %0" ::"m"(gdtr));
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// Save the contents of MSR_GS_BASE, as they get cleared by a write to `gs`.
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uintptr_t gs = asm_rdmsr(MSR_GS_BASE);
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// Flush and reload the segment registers.
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asm volatile(
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"push %0\n"
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"lea rax, [rip + 1f]\n"
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"push rax\n"
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"retfq\n"
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"1:\n"
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"mov ax, %1\n"
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"mov ds, ax\n"
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"mov es, ax\n"
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"mov fs, ax\n"
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"mov gs, ax\n"
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"mov ss, ax\n"
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:
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: "i"(offsetof(struct gdt, kernel_code64)), "i"(offsetof(struct gdt, kernel_data64))
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: "rax", "memory"
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);
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asm_wrmsr(MSR_GS_BASE, gs);
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asm volatile(
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"mov ax, %c0\n"
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"ltr ax"
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:
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: "i"(offsetof(struct gdt, tss))
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: "rax", "memory"
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);
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}
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