256 lines
6.2 KiB
C
256 lines
6.2 KiB
C
#pragma once
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#include <stdint.h>
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enum : uint32_t {
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CPUID_1C_SSE3 = 1u << 0,
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CPUID_1C_PCLMUL = 1u << 1,
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CPUID_1C_DTES64 = 1u << 2,
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CPUID_1C_MONITOR = 1u << 3,
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CPUID_1C_DS_CPL = 1u << 4,
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CPUID_1C_VMX = 1u << 5,
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CPUID_1C_SMX = 1u << 6,
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CPUID_1C_EST = 1u << 7,
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CPUID_1C_TM2 = 1u << 8,
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CPUID_1C_SSSE3 = 1u << 9,
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CPUID_1C_CID = 1u << 10,
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CPUID_1C_SDBG = 1u << 11,
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CPUID_1C_FMA = 1u << 12,
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CPUID_1C_CX16 = 1u << 13,
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CPUID_1C_XTPR = 1u << 14,
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CPUID_1C_PDCM = 1u << 15,
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CPUID_1C_PCID = 1u << 17,
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CPUID_1C_DCA = 1u << 18,
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CPUID_1C_SSE4_1 = 1u << 19,
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CPUID_1C_SSE4_2 = 1u << 20,
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CPUID_1C_X2APIC = 1u << 21,
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CPUID_1C_MOVBE = 1u << 22,
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CPUID_1C_POPCNT = 1u << 23,
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CPUID_1C_TSC = 1u << 24,
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CPUID_1C_AES = 1u << 25,
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CPUID_1C_XSAVE = 1u << 26,
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CPUID_1C_OSXSAVE = 1u << 27,
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CPUID_1C_AVX = 1u << 28,
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CPUID_1C_F16C = 1u << 29,
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CPUID_1C_RDRAND = 1u << 30,
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CPUID_1C_HYPERVISOR = 1u << 31,
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};
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enum : uint32_t {
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CPUID_1D_FPU = 1u << 0,
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CPUID_1D_VME = 1u << 1,
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CPUID_1D_DE = 1u << 2,
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CPUID_1D_PSE = 1u << 3,
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CPUID_1D_TSC = 1u << 4,
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CPUID_1D_MSR = 1u << 5,
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CPUID_1D_PAE = 1u << 6,
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CPUID_1D_MCE = 1u << 7,
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CPUID_1D_CX8 = 1u << 8,
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CPUID_1D_APIC = 1u << 9,
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CPUID_1D_SEP = 1u << 11,
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CPUID_1D_MTRR = 1u << 12,
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CPUID_1D_PGE = 1u << 13,
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CPUID_1D_MCA = 1u << 14,
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CPUID_1D_CMOV = 1u << 15,
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CPUID_1D_PAT = 1u << 16,
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CPUID_1D_PSE36 = 1u << 17,
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CPUID_1D_PSN = 1u << 18,
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CPUID_1D_CLFLUSH = 1u << 19,
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CPUID_1D_DS = 1u << 21,
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CPUID_1D_ACPI = 1u << 22,
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CPUID_1D_MMX = 1u << 23,
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CPUID_1D_FXSR = 1u << 24,
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CPUID_1D_SSE = 1u << 25,
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CPUID_1D_SSE2 = 1u << 26,
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CPUID_1D_SS = 1u << 27,
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CPUID_1D_HTT = 1u << 28,
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CPUID_1D_TM = 1u << 29,
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CPUID_1D_IA64 = 1u << 30,
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CPUID_1D_PBE = 1u << 31,
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};
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enum : uint32_t {
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CPUID_7B_FSGSBASE = 1u << 0,
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CPUID_7B_SGX = 1u << 2,
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CPUID_7B_BMI = 1u << 3,
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CPUID_7B_HLE = 1u << 4,
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CPUID_7B_AVX2 = 1u << 5,
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CPUID_7B_SMEP = 1u << 7,
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CPUID_7B_BMI2 = 1u << 8,
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CPUID_7B_RTM = 1u << 11,
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CPUID_7B_AVX512F = 1u << 16,
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CPUID_7B_AVX512DQ = 1u << 17,
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CPUID_7B_RDSEED = 1u << 18,
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CPUID_7B_ADX = 1u << 19,
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CPUID_7B_SMAP = 1u << 20,
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CPUID_7B_AVX512IFMA = 1u << 21,
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CPUID_7B_CLFLUSHOPT = 1u << 23,
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CPUID_7B_CLWB = 1u << 24,
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CPUID_7B_AVX512CD = 1u << 28,
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CPUID_7B_SHA = 1u << 29,
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CPUID_7B_AVX512BW = 1u << 30,
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CPUID_7B_AVX512VL = 1u << 31,
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};
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enum : uint32_t {
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CPUID_7C_AVX512VBMI = 1u << 1,
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CPUID_7C_UMIP = 1u << 2,
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CPUID_7C_PKU = 1u << 3,
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CPUID_7C_OSPKE = 1u << 4,
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CPUID_7C_WAITPKG = 1u << 5,
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CPUID_7C_AVX512VBMI2 = 1u << 6,
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CPUID_7C_SHSTK = 1u << 7,
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CPUID_7C_GFNI = 1u << 8,
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CPUID_7C_VAES = 1u << 9,
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CPUID_7C_VPCLMULQDQ = 1u << 10,
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CPUID_7C_AVX512VNNI = 1u << 11,
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CPUID_7C_AVX512BITALG = 1u << 12,
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CPUID_7C_TME_EN = 1u << 13,
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CPUID_7C_AVX512VPOPCNTDQ = 1u << 14,
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CPUID_7C_RDPID = 1u << 22,
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CPUID_7C_KL = 1u << 23,
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CPUID_7C_CLDEMOTE = 1u << 25,
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CPUID_7C_MOVDIRI = 1u << 27,
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CPUID_7C_MOVDIR64B = 1u << 28,
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CPUID_7C_ENQCMD = 1u << 29,
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};
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enum : uint32_t {
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CPUID_7D_UINTR = 1u << 5,
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CPUID_7D_AVX512VP2INTERSECT = 1u << 8,
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CPUID_7D_SERIALIZE = 1u << 14,
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CPUID_7D_TSXLDTRK = 1u << 16,
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CPUID_7D_PCONFIG = 1u << 18,
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CPUID_7D_IBT = 1u << 20,
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CPUID_7D_AMX_BF16 = 1u << 22,
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CPUID_7D_AVX512FP16 = 1u << 23,
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CPUID_7D_AMX_TILE = 1u << 24,
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CPUID_7D_AMX_INT8 = 1u << 25,
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};
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enum : uint64_t {
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RFLAGS_CF = 1ull << 0,
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RFLAGS_BRKI = 1ull << 1,
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RFLAGS_PF = 1ull << 2,
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RFLAGS_AF = 1ull << 4,
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RFLAGS_ZF = 1ull << 6,
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RFLAGS_SF = 1ull << 7,
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RFLAGS_TF = 1ull << 8,
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RFLAGS_IF = 1ull << 9,
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RFLAGS_DF = 1ull << 10,
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RFLAGS_OF = 1ull << 11,
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RFLAGS_IOPL = 3ull << 12,
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RFLAGS_NT = 1ull << 14,
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RFLAGS_RF = 1ull << 16,
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RFLAGS_VM = 1ull << 17,
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RFLAGS_AC = 1ull << 18,
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RFLAGS_VIF = 1ull << 19,
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RFLAGS_VIP = 1ull << 20,
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RFLAGS_ID = 1ull << 21,
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};
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enum : uint64_t {
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XCR0_X87 = 1ull << 0,
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XCR0_SSE = 1ull << 1,
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XCR0_AVX = 1ull << 2,
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XCR0_AXV512_OPMASK = 1ull << 5,
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XCR0_AVX512_ZMM_HI256 = 1ull << 6,
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XCR0_AVX512_HI16_ZMM = 1ull << 7,
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};
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enum : uint64_t {
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CR0_PE = 1ull << 0,
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CR0_MP = 1ull << 1,
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CR0_EM = 1ull << 2,
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CR0_TS = 1ull << 3,
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CR0_ET = 1ull << 4,
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CR0_NE = 1ull << 5,
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CR0_WP = 1ull << 16,
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CR0_AM = 1ull << 18,
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CR0_NW = 1ull << 29,
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CR0_CD = 1ull << 30,
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CR0_PG = 1ull << 31,
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};
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enum : uint64_t {
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CR4_VME = 1ull << 0,
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CR4_PVI = 1ull << 1,
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CR4_TSD = 1ull << 2,
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CR4_DE = 1ull << 3,
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CR4_PSE = 1ull << 4,
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CR4_PAE = 1ull << 5,
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CR4_MCE = 1ull << 6,
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CR4_PGE = 1ull << 7,
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CR4_PCE = 1ull << 8,
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CR4_OSFXSR = 1ull << 9,
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CR4_OSXMMEXCPT = 1ull << 10,
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CR4_UMIP = 1ull << 11,
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CR4_VMXE = 1ull << 13,
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CR4_SMXE = 1ull << 14,
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CR4_FSGSBASE = 1ull << 16,
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CR4_PCIDE = 1ull << 17,
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CR4_OSXSAVE = 1ull << 18,
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CR4_SMEP = 1ull << 20,
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CR4_SMAP = 1ull << 21,
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CR4_PKE = 1ull << 22,
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CR4_CET = 1ull << 23,
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CR4_PKS = 1ull << 24,
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};
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enum : uint64_t {
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MSR_EFER_SCE = 1ull << 0,
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MSR_EFER_LME = 1ull << 8,
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MSR_EFER_LMA = 1ull << 10,
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MSR_EFER_NXE = 1ull << 11,
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MSR_EFER_SVME = 1ull << 12,
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MSR_EFER_LMSLE = 1ull << 13,
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MSR_EFER_FFXSR = 1ull << 14,
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MSR_EFER_TCE = 1ull << 15,
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};
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enum : uint32_t {
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MSR_PAT = 0x277,
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MSR_EFER = 0xC0000080,
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MSR_STAR = 0xC0000081,
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MSR_LSTAR = 0xC0000082,
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MSR_CSTAR = 0xC0000083,
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MSR_SFMASK = 0xC0000084,
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MSR_FS_BASE = 0xC0000100,
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MSR_GS_BASE = 0xC0000101,
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MSR_KERNEL_GS_BASE = 0xC0000102,
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};
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enum : uint8_t {
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PAT_UC = 0x0,
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PAT_WC = 0x1,
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PAT_WT = 0x4,
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PAT_WP = 0x5,
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PAT_WB = 0x6,
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PAT_UCM = 0x7,
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};
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enum : uint8_t {
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CPL_USER = 0x3,
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CPL_KERNEL = 0x0,
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};
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enum : uint8_t {
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IDT_DE = 0x0,
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IDT_DB = 0x1,
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IDT_BP = 0x3,
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IDT_OF = 0x4,
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IDT_BR = 0x5,
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IDT_UD = 0x6,
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IDT_NM = 0x7,
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IDT_SS = 0xC,
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IDT_GP = 0xD,
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IDT_PF = 0xE,
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IDT_MF = 0x10,
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IDT_AC = 0x11,
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IDT_XM = 0x13,
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IDT_IPI_SHOOTDOWN = 0xFC,
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IDT_TIMER = 0xFD,
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IDT_SPURIOUS = 0xFE,
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IDT_IPI_RESCHED = 0xFF,
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};
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