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https://github.com/Mathewnd/Astral.git
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cpu: add irq depth counting
Add a way of checking if a cpu is in the middle of handling an irq and how deep it is into it. This will allow for future code to conditionally run only in/outside interrupts.
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@@ -45,6 +45,7 @@ static void dopending(context_t *ctx, void *) {
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arch_interrupt_disable();
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bool entrystatus = current_cpu()->intstatus;
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current_cpu()->intstatus = false;
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__atomic_fetch_add(¤t_cpu()->irq_depth, 1, __ATOMIC_RELAXED);
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isr_t *list = NULL;
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isr_t *iterator = current_cpu()->isrqueue;
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@@ -87,18 +88,25 @@ static void dopending(context_t *ctx, void *) {
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}
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cleanup:
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__atomic_fetch_sub(¤t_cpu()->irq_depth, 1, __ATOMIC_RELAXED);
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if (entrystatus) {
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current_cpu()->intstatus = true;
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arch_interrupt_enable();
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}
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}
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__attribute__((no_caller_saved_registers)) void sched_userspacecheck(context_t *context, bool syscall, uint64_t syscallret, uint64_t syscallerrno);
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__attribute__((no_caller_saved_registers)) void sched_userspacecheck(context_t *context,
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bool syscall,
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uint64_t syscallret,
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uint64_t syscallerrno);
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void interrupt_isr(int vec, context_t *ctx) {
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isr_t *isr = ¤t_cpu()->isr[vec];
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current_cpu()->intstatus = false;
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if (isr->priority != IPL_IGNORE)
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__atomic_fetch_add(¤t_cpu()->irq_depth, 1, __ATOMIC_RELAXED);
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if (isr->func == NULL) {
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char oops[64];
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snprintf(oops, 64, "Unregistered interrupt %d\n", vec);
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@@ -116,6 +124,9 @@ void interrupt_isr(int vec, context_t *ctx) {
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if (isr->eoi)
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isr->eoi(isr);
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if (isr->priority != IPL_IGNORE)
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__atomic_fetch_sub(¤t_cpu()->irq_depth, 1, __ATOMIC_RELAXED);
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if (ARCH_CONTEXT_ISUSER(ctx))
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sched_userspacecheck(ctx, false, 0, 0);
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