mirror of
https://github.com/Mathewnd/Astral.git
synced 2026-10-31 06:28:22 +00:00
u80211_drv: port over rtl8188eu driver
This commit is contained in:
Matheus
@@ -0,0 +1,37 @@
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#ifndef U80211_DRV_80211_H
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#define U80211_DRV_80211_H
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#include <stdint.h>
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#include <u80211_drv/util.h>
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#define U80211_DRV_80211_FRAME_TYPE_MANAGEMENT 0
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#define U80211_DRV_80211_FRAME_TYPE_DATA 2
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#define U80211_DRV_80211_FRAME_DATA_QOS_BIT 0x8
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#define U80211_DRV_80211_HEADER_MINIMUM_SIZE 24
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#define U80211_DRV_80211_MAX_MPDU_SIZE 2352
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static inline uint16_t u80211_drv_80211_frame_control(const void *frame) {
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return u80211_drv_deserialize_le16(frame);
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}
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static inline uint8_t u80211_drv_80211_frame_type(uint16_t frame_control) {
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return (frame_control >> 2) & 0x3;
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}
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static inline uint8_t u80211_drv_80211_frame_subtype(uint16_t frame_control) {
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return (frame_control >> 4) & 0xf;
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}
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static inline const uint8_t *u80211_drv_80211_receiver_address(const void *frame) {
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const uint8_t *frame_bytes = frame;
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return frame_bytes + 4;
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}
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static inline uint16_t u80211_drv_80211_sequence_number(const void *frame) {
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const uint8_t *frame_bytes = frame;
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return u80211_drv_deserialize_le16(frame_bytes + 22) >> 4;
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}
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#endif
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@@ -0,0 +1,8 @@
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#ifndef U80211_DRV_DRV_INIT_H
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#define U80211_DRV_DRV_INIT_H
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#include <u80211_drv/kernel_interface.h>
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int u80211_drv_rtl8188eu_init(u80211_drv_device_handle_t device, u80211_drv_interface_handle_t interface);
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#endif
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@@ -0,0 +1,171 @@
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#ifndef U80211_DRV_KERNEL_INTERFACE_H
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#define U80211_DRV_KERNEL_INTERFACE_H
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#include <stddef.h>
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#include <stdint.h>
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// opaque handles supplied by the kernel integration
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// the driver only stores and passes these handles back to the integration
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typedef void *u80211_drv_device_handle_t;
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typedef void *u80211_drv_interface_handle_t;
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typedef void *u80211_drv_transfer_handle_t;
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typedef void *u80211_drv_network_device_handle_t;
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typedef void (*u80211_drv_kernel_transfer_callback_t)(void *context, int status, size_t transferred_size);
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// usb device descriptor fields used to match a driver
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typedef struct {
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uint16_t vendor_id;
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uint16_t product_id;
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} u80211_drv_device_descriptor_t;
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// usb interface descriptor fields used to match a driver and discover its endpoints
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typedef struct {
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uint8_t number;
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uint8_t class_code;
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uint8_t subclass;
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uint8_t protocol;
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uint8_t endpoint_count;
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} u80211_drv_interface_descriptor_t;
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// usb endpoint descriptor fields required by a driver
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typedef struct {
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uint8_t address;
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uint8_t attributes;
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uint16_t maximum_packet_size;
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uint8_t interval;
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} u80211_drv_endpoint_descriptor_t;
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#define U80211_DRV_DEVICE_MAC_ADDRESS_LEN 6
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#define U80211_DRV_DEVICE_RATE_BITMAP_LEN 16
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// radio properties published once initialization has completed
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typedef struct {
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uint8_t mac_address[U80211_DRV_DEVICE_MAC_ADDRESS_LEN];
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// bit N represents a supported rate of N * 500 kbit/s
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uint8_t rate_bitmap[U80211_DRV_DEVICE_RATE_BITMAP_LEN];
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} u80211_drv_device_metadata_t;
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// cipher values used by key installation and transmission
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#define U80211_DRV_CIPHER_NONE -1
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#define U80211_DRV_CIPHER_CCMP 0
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#define U80211_DRV_CIPHER_TKIP 1
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#define U80211_DRV_CIPHER_WEP40 2
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#define U80211_DRV_CIPHER_WEP104 3
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#define U80211_DRV_KEY_PAIRWISE (1u << 0)
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#define U80211_DRV_KEY_GROUP (1u << 1)
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#define U80211_DRV_KEY_RX (1u << 2)
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#define U80211_DRV_KEY_TX (1u << 3)
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// key data passed to set_key
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typedef struct {
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int cipher;
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uint8_t index;
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uint8_t peer[U80211_DRV_DEVICE_MAC_ADDRESS_LEN];
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const uint8_t *key;
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size_t key_len;
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uint32_t flags;
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} u80211_drv_key_t;
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// per-packet encryption selection
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// key is the installed key index or -1 when no key is selected
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// cipher is one of U80211_DRV_CIPHER_*
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typedef struct {
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int key;
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int cipher;
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} u80211_drv_transmit_options_t;
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// operations implemented by a hardware driver and published through u80211_drv_device_ready()
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// unless otherwise stated operations return a U80211_DRV_STATUS_* value
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typedef struct {
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// allocates a buffer of 'size' bytes
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// on success '*buffer' points at the start of the writable 802.11 frame region
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int (*allocate_tx_buffer)(size_t size, void **buffer);
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void (*free_tx_buffer)(void *buffer);
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// transmits the bytes and consumes buffer including on failure
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int (*transmit)(void *device, void *buffer, size_t size, size_t current_offset, const u80211_drv_transmit_options_t *options);
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// sets the rf channel number the device will rx/tx on
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int (*set_channel)(void *device, uint8_t channel);
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// adds an encryption key
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int (*set_key)(void *device, const u80211_drv_key_t *key);
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// deletes an encryption ke
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int (*del_key)(void *device, uint8_t index);
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} u80211_drv_device_ops_t;
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// values used to control usb transfers
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#define U80211_DRV_KERNEL_XFER_OUT 0x00
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#define U80211_DRV_KERNEL_XFER_IN 0x80
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#define U80211_DRV_KERNEL_XFER_DIRECTION_MASK 0x80
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#define U80211_DRV_KERNEL_ENDPOINT_TRANSFER_TYPE_MASK 0x03
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#define U80211_DRV_KERNEL_ENDPOINT_TRANSFER_TYPE_BULK 0x02
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#define U80211_DRV_KERNEL_XFER_REQUEST_TYPE_STANDARD 0x00
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#define U80211_DRV_KERNEL_XFER_REQUEST_TYPE_CLASS 0x20
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#define U80211_DRV_KERNEL_XFER_REQUEST_TYPE_VENDOR 0x40
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#define U80211_DRV_KERNEL_XFER_REQUEST_TYPE_RESERVED 0x60
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#define U80211_DRV_KERNEL_XFER_REQUEST_TYPE_MASK 0x60
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#define U80211_DRV_KERNEL_XFER_RECIPIENT_DEVICE 0x00
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#define U80211_DRV_KERNEL_XFER_RECIPIENT_INTERFACE 0x01
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#define U80211_DRV_KERNEL_XFER_RECIPIENT_ENDPOINT 0x02
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#define U80211_DRV_KERNEL_XFER_RECIPIENT_OTHER 0x03
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#define U80211_DRV_KERNEL_XFER_RECIPIENT_MASK 0x1f
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#define U80211_DRV_KERNEL_PRINT_LEVEL_INFO 0
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#define U80211_DRV_KERNEL_PRINT_LEVEL_WARN 1
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#define U80211_DRV_KERNEL_PRINT_LEVEL_ERROR 2
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// allocates 'size' bytes of memory
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// return NULL on allocation failure
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void *u80211_drv_kernel_allocate(size_t size);
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// frees the kernel memory referenced by 'memory'
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// 'memory' will never be NULL
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void u80211_drv_kernel_free(void *memory);
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// requests for firmware to be loaded
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// invokes callback once firmware is available
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// the callback must not be invoked on failure
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// 'firmware_data' only needs to be valid for the duration of the callback
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typedef void (*u80211_drv_kernel_firmware_callback_t)(void *context, const void *firmware_data, size_t firmware_size);
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int u80211_drv_kernel_get_firmware(const char *name, u80211_drv_kernel_firmware_callback_t callback, void *context);
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// these functions return usb descriptors into the specified buffers
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int u80211_drv_kernel_get_device_descriptor(u80211_drv_device_handle_t device, u80211_drv_device_descriptor_t *descriptor);
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int u80211_drv_kernel_get_interface_descriptor(u80211_drv_interface_handle_t interface, u80211_drv_interface_descriptor_t *descriptor);
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int u80211_drv_kernel_get_endpoints(u80211_drv_interface_handle_t interface, u80211_drv_endpoint_descriptor_t *endpoints, size_t endpoint_count);
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// synchronous usb control transfers with a timeout in milliseconds
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// 'flags' combines U80211_DRV_KERNEL_XFER_* values into the usb control request type
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int u80211_drv_kernel_submit_control_xfer_and_wait(u80211_drv_device_handle_t device, uint8_t flags, uint8_t request, uint16_t value, uint16_t index, void *buf, uint16_t buffer_size, size_t *transferred_size, unsigned int timeout);
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// synchronous usb bulk transfers with a timeout in milliseconds
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int u80211_drv_kernel_submit_bulk_xfer_and_wait(u80211_drv_device_handle_t device, uint8_t endpoint_address, void *buf, size_t buffer_size, size_t *transferred_size, unsigned int timeout);
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// allocates a reusable asynchronous bulk transfer
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// 'buffer' and 'context' must stay valid across submissions and callbacks
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// callback receives a U80211_DRV_STATUS_* value and zero transferred_size on failure
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// a completed transfer may be submitted again from its callback
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int u80211_drv_kernel_allocate_bulk_xfer(u80211_drv_device_handle_t device, uint8_t endpoint_address, void *buffer, size_t buffer_size, u80211_drv_kernel_transfer_callback_t callback, void *context, u80211_drv_transfer_handle_t *transfer);
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// starts an asynchronous transfer
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// submitting one that is already active must return U80211_DRV_STATUS_INVALID_ARGUMENT
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int u80211_drv_kernel_submit_xfer(u80211_drv_transfer_handle_t transfer);
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// busy-waits for at least 'microseconds' before returning
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void u80211_drv_kernel_stall_us(unsigned int microseconds);
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// writes one complete message at the requested U80211_DRV_KERNEL_PRINT_LEVEL_*
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void u80211_drv_kernel_print(int level, const char *msg);
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// publishes an initialized radio to the kernel integration
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// 'network_device' receives the handle used for received packets
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int u80211_drv_device_ready(void *device, const u80211_drv_device_metadata_t *metadata, const u80211_drv_device_ops_t *ops, u80211_drv_network_device_handle_t *network_device);
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// delivers one 802.11 packet
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// might be called from an interrupt context
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void u80211_drv_packet_received(u80211_drv_network_device_handle_t device, void *packet, size_t packet_size);
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#endif
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@@ -0,0 +1,389 @@
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#ifndef U80211_DRV_RTL8188EU_H
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#define U80211_DRV_RTL8188EU_H
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <u80211_drv/kernel_interface.h>
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#define U80211_DRV_RTL8188EU_REG_SYS_ISO_CTRL 0x0000
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#define U80211_DRV_RTL8188EU_REG_SYS_ISO_CTRL_PWC_EV12V (1u << 15)
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#define U80211_DRV_RTL8188EU_REG_SYS_FUNC 0x0002
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#define U80211_DRV_RTL8188EU_REG_SYS_FUNC_BBRSTB (1u << 0)
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#define U80211_DRV_RTL8188EU_REG_SYS_FUNC_BB_GLB_RSTN (1u << 1)
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#define U80211_DRV_RTL8188EU_REG_SYS_FUNC_USBA (1u << 2)
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#define U80211_DRV_RTL8188EU_REG_SYS_FUNC_USBD (1u << 4)
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#define U80211_DRV_RTL8188EU_REG_SYS_FUNC_CPUEN (1u << 10)
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#define U80211_DRV_RTL8188EU_REG_SYS_FUNC_ELDR (1u << 12)
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#define U80211_DRV_RTL8188EU_REG_SYS_FUNC_DIO_RF (1u << 13)
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#define U80211_DRV_RTL8188EU_REG_APS_FSMCO 0x0004
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#define U80211_DRV_RTL8188EU_REG_APS_FSMCO_MAC_ENABLE (1u << 8)
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#define U80211_DRV_RTL8188EU_REG_APS_FSMCO_HW_SUSPEND (1u << 11)
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#define U80211_DRV_RTL8188EU_REG_APS_FSMCO_PCIE (1u << 12)
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#define U80211_DRV_RTL8188EU_REG_APS_FSMCO_HW_POWERDOWN (1u << 15)
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#define U80211_DRV_RTL8188EU_REG_APS_FSMCO_POWER_READY (1u << 17)
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#define U80211_DRV_RTL8188EU_REG_SYS_CLKR 0x0008
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#define U80211_DRV_RTL8188EU_REG_SYS_CLKR_ANA8M (1u << 1)
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#define U80211_DRV_RTL8188EU_REG_SYS_CLKR_LOADER_ENABLE (1u << 5)
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#define U80211_DRV_RTL8188EU_REG_9346CR 0x000a
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#define U80211_DRV_RTL8188EU_REG_9346CR_EEPROM_BOOT (1u << 4)
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#define U80211_DRV_RTL8188EU_REG_9346CR_EEPROM_ENABLE (1u << 5)
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#define U80211_DRV_RTL8188EU_REG_RSV_CTRL 0x001c
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#define U80211_DRV_RTL8188EU_REG_RSV_CTRL_WLOCK_00 (1u << 1)
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#define U80211_DRV_RTL8188EU_REG_RSV_CTRL_MCU_RST (1u << 11)
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#define U80211_DRV_RTL8188EU_REG_RF_CTRL 0x001f
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#define U80211_DRV_RTL8188EU_REG_RF_CTRL_ENABLE (1u << 0)
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#define U80211_DRV_RTL8188EU_REG_RF_CTRL_RSTB (1u << 1)
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#define U80211_DRV_RTL8188EU_REG_RF_CTRL_SDMRSTB (1u << 2)
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#define U80211_DRV_RTL8188EU_REG_LPLDO_CTRL 0x0023
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#define U80211_DRV_RTL8188EU_REG_LPLDO_CTRL_SLEEP (1u << 4)
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#define U80211_DRV_RTL8188EU_REG_AFE_XTAL_CTRL 0x0024
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#define U80211_DRV_RTL8188EU_REG_AFE_XTAL_CTRL_SCHMITT_TRIGGER (1u << 23)
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#define U80211_DRV_RTL8188EU_REG_AFE_XTAL_CTRL_ADDRESS_MASK 0x007ff800
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#define U80211_DRV_RTL8188EU_REG_AFE_XTAL_CTRL_ADDRESS_SHIFT 11
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#define U80211_DRV_RTL8188EU_REG_EFUSE_CTRL 0x0030
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#define U80211_DRV_RTL8188EU_REG_EFUSE_CTRL_READ_READY (1u << 31)
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#define U80211_DRV_RTL8188EU_REG_LEDCFG2 0x004e
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#define U80211_DRV_RTL8188EU_REG_LEDCFG2_HW_LED_CONTROL (1u << 1)
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#define U80211_DRV_RTL8188EU_REG_LEDCFG2_SW_LED_DISABLE (1u << 3)
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#define U80211_DRV_RTL8188EU_REG_LEDCFG2_HW_LED_ENABLE (1u << 5)
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#define U80211_DRV_RTL8188EU_REG_EFUSE_ACCESS 0x00cf
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#define U80211_DRV_RTL8188EU_EFUSE_ACCESS_ENABLE 0x69
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#define U80211_DRV_RTL8188EU_EFUSE_ACCESS_DISABLE 0x00
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#define U80211_DRV_RTL8188EU_REG_MCUFWDL 0x0080
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#define U80211_DRV_RTL8188EU_REG_MCUFWDL_ENABLE (1u << 0)
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#define U80211_DRV_RTL8188EU_REG_MCUFWDL_READY (1u << 1)
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#define U80211_DRV_RTL8188EU_REG_MCUFWDL_CHECKSUM_REPORT (1u << 2)
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#define U80211_DRV_RTL8188EU_REG_MCUFWDL_WINTINI_READY (1u << 6)
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#define U80211_DRV_RTL8188EU_REG_MCUFWDL_RAM_DOWNLOAD_SELECT (1u << 7)
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#define U80211_DRV_RTL8188EU_REG_MCUFWDL_PAGE_MASK (7u << 16)
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#define U80211_DRV_RTL8188EU_REG_MCUFWDL_ROM_DOWNLOAD_LENGTH (1u << 19)
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#define U80211_DRV_RTL8188EU_FIRMWARE_START_ADDRESS 0x1000
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#define U80211_DRV_RTL8188EU_FIRMWARE_PAGE_SIZE 4096
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#define U80211_DRV_RTL8188EU_FIRMWARE_HEADER_SIZE 32
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#define U80211_DRV_RTL8188EU_EFUSE_PHYSICAL_LEN 512
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#define U80211_DRV_RTL8188EU_EFUSE_MAP_LEN 512
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#define U80211_DRV_RTL8188EU_EFUSE_WORDS_PER_SECTION 4
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#define U80211_DRV_RTL8188EU_EFUSE_RTL_ID 0x8129
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#define U80211_DRV_RTL8188EU_MAC_ADDRESS_LEN 6
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#define U80211_DRV_RTL8188EU_CCK_TX_POWER_BASE_INDEX_COUNT 6
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#define U80211_DRV_RTL8188EU_HT40_1S_TX_POWER_BASE_INDEX_COUNT 5
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#define U80211_DRV_RTL8188EU_REG_SYS_CFG 0xf0
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#define U80211_DRV_RTL8188EU_REG_SYS_CFG_TRP_VAUX_EN (1u << 23)
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#define U80211_DRV_RTL8188EU_REG_SYS_CFG_VER(value) (((value) >> 12) & 0xfu)
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#define U80211_DRV_RTL8188EU_REG_CR 0x0100
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#define U80211_DRV_RTL8188EU_REG_CR_HCI_TXDMA_ENABLE (1u << 0)
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#define U80211_DRV_RTL8188EU_REG_CR_HCI_RXDMA_ENABLE (1u << 1)
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#define U80211_DRV_RTL8188EU_REG_CR_TXDMA_ENABLE (1u << 2)
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#define U80211_DRV_RTL8188EU_REG_CR_RXDMA_ENABLE (1u << 3)
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#define U80211_DRV_RTL8188EU_REG_CR_PROTOCOL_ENABLE (1u << 4)
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#define U80211_DRV_RTL8188EU_REG_CR_SCHEDULE_ENABLE (1u << 5)
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#define U80211_DRV_RTL8188EU_REG_CR_MAC_TX_ENABLE (1u << 6)
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#define U80211_DRV_RTL8188EU_REG_CR_MAC_RX_ENABLE (1u << 7)
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#define U80211_DRV_RTL8188EU_REG_CR_SECURITY_ENABLE (1u << 9)
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#define U80211_DRV_RTL8188EU_REG_CR_CALTIMER_ENABLE (1u << 10)
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#define U80211_DRV_RTL8188EU_REG_MSR 0x0102
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#define U80211_DRV_RTL8188EU_REG_MSR_NETWORK_TYPE_MASK 0x03
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#define U80211_DRV_RTL8188EU_REG_PBP 0x0104
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#define U80211_DRV_RTL8188EU_REG_PBP_128_BYTES 0x11
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#define U80211_DRV_RTL8188EU_REG_TRXDMA_CTRL 0x010c
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#define U80211_DRV_RTL8188EU_REG_TRXDMA_CTRL_VO_SHIFT 4
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#define U80211_DRV_RTL8188EU_REG_TRXDMA_CTRL_VI_SHIFT 6
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#define U80211_DRV_RTL8188EU_REG_TRXDMA_CTRL_BE_SHIFT 8
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#define U80211_DRV_RTL8188EU_REG_TRXDMA_CTRL_BK_SHIFT 10
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#define U80211_DRV_RTL8188EU_REG_TRXDMA_CTRL_MG_SHIFT 12
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#define U80211_DRV_RTL8188EU_REG_TRXDMA_CTRL_HI_SHIFT 14
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#define U80211_DRV_RTL8188EU_REG_TRXDMA_CTRL_LOW_CONTROL_MASK 0x0007
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#define U80211_DRV_RTL8188EU_REG_TRXDMA_CTRL_RXDMA_AGG_ENABLE (1u << 2)
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#define U80211_DRV_RTL8188EU_REG_TRXFF_BNDY 0x0114
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#define U80211_DRV_RTL8188EU_RX_FIFO_BOUNDARY 0x25ff
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#define U80211_DRV_RTL8188EU_REG_LLT_INIT 0x01e0
|
||||
#define U80211_DRV_RTL8188EU_REG_LLT_INIT_OP_WRITE (1u << 30)
|
||||
#define U80211_DRV_RTL8188EU_REG_LLT_INIT_OP_MASK (3u << 30)
|
||||
#define U80211_DRV_RTL8188EU_LLT_LAST_ENTRY 0xaf
|
||||
#define U80211_DRV_RTL8188EU_LLT_END 0xff
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_RQPN 0x0200
|
||||
#define U80211_DRV_RTL8188EU_REG_RQPN_HI_SHIFT 0
|
||||
#define U80211_DRV_RTL8188EU_REG_RQPN_LO_SHIFT 8
|
||||
#define U80211_DRV_RTL8188EU_REG_RQPN_PUB_SHIFT 16
|
||||
#define U80211_DRV_RTL8188EU_REG_RQPN_LOAD (1u << 31)
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_RQPN_NPQ 0x0214
|
||||
#define U80211_DRV_RTL8188EU_REG_RQPN_NPQ_SHIFT 0
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_TDECTRL 0x0208
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_FWHW_TXQ_CTRL 0x0420
|
||||
#define U80211_DRV_RTL8188EU_REG_FWHW_TXQ_CTRL_AMPDU_RTY_NEW (1u << 7)
|
||||
#define U80211_DRV_RTL8188EU_REG_HWSEQ_CTRL 0x0423
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_SPEC_SIFS 0x0428
|
||||
#define U80211_DRV_RTL8188EU_REG_RL 0x042a
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_RRSR 0x0440
|
||||
#define U80211_DRV_RTL8188EU_REG_RRSR_RATE_MASK 0x000fffff
|
||||
#define U80211_DRV_RTL8188EU_REG_RRSR_RATE_CCK_ONLY_1M 0x000ffff1
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_TXPKTBUF_BCNQ_BDNY 0x0424
|
||||
#define U80211_DRV_RTL8188EU_REG_TXPKTBUF_MGQ_BDNY 0x0425
|
||||
#define U80211_DRV_RTL8188EU_REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_MAX_AGGR_NUM 0x04ca
|
||||
#define U80211_DRV_RTL8188EU_REG_MAX_AGGR_NUM_8188EU 0x07
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_EDCA_VO 0x0500
|
||||
#define U80211_DRV_RTL8188EU_REG_EDCA_VI 0x0504
|
||||
#define U80211_DRV_RTL8188EU_REG_EDCA_BE 0x0508
|
||||
#define U80211_DRV_RTL8188EU_REG_EDCA_BK 0x050c
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_BCNTCFG 0x0510
|
||||
#define U80211_DRV_RTL8188EU_REG_SIFS_CCK 0x0514
|
||||
#define U80211_DRV_RTL8188EU_REG_SIFS_OFDM 0x0516
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_TBTT_PROHIBIT 0x0540
|
||||
#define U80211_DRV_RTL8188EU_REG_BCN_CTRL 0x0550
|
||||
#define U80211_DRV_RTL8188EU_REG_DRVERLYINT 0x0558
|
||||
#define U80211_DRV_RTL8188EU_REG_BCNDMATIM 0x0559
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_BWOPMODE 0x0603
|
||||
#define U80211_DRV_RTL8188EU_REG_BWOPMODE_20MHZ (1u << 2)
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_RCR 0x0608
|
||||
#define U80211_DRV_RTL8188EU_REG_RCR_AAP (1u << 0)
|
||||
#define U80211_DRV_RTL8188EU_REG_RCR_APM (1u << 1)
|
||||
#define U80211_DRV_RTL8188EU_REG_RCR_AM (1u << 2)
|
||||
#define U80211_DRV_RTL8188EU_REG_RCR_AB (1u << 3)
|
||||
#define U80211_DRV_RTL8188EU_REG_RCR_AMF (1u << 13)
|
||||
#define U80211_DRV_RTL8188EU_REG_RCR_HTC_LOC_CTRL (1u << 14)
|
||||
#define U80211_DRV_RTL8188EU_REG_RCR_APP_PHYSTS (1u << 28)
|
||||
#define U80211_DRV_RTL8188EU_REG_RCR_APP_ICV (1u << 29)
|
||||
#define U80211_DRV_RTL8188EU_REG_RCR_APP_MIC (1u << 30)
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_RX_DRVINFO_SZ 0x060f
|
||||
#define U80211_DRV_RTL8188EU_RX_DRVINFO_SZ 4
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_MACID 0x0610
|
||||
#define U80211_DRV_RTL8188EU_REG_MAR 0x0620
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_MAC_SPEC_SIFS 0x063a
|
||||
#define U80211_DRV_RTL8188EU_REG_RESP_SIFS_CCK 0x063c
|
||||
#define U80211_DRV_RTL8188EU_REG_RESP_SIFS_OFDM 0x063e
|
||||
#define U80211_DRV_RTL8188EU_REG_ACKTO 0x0640
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_CAMCMD 0x0670
|
||||
#define U80211_DRV_RTL8188EU_REG_CAMWRITE 0x0674
|
||||
#define U80211_DRV_RTL8188EU_REG_CAMCMD_WRITE (1u << 16)
|
||||
#define U80211_DRV_RTL8188EU_REG_CAMCMD_CLR (1u << 30)
|
||||
#define U80211_DRV_RTL8188EU_REG_CAMCMD_POLLING (1u << 31)
|
||||
|
||||
#define U80211_DRV_RTL8188EU_CAM_ENTRY_WORD_COUNT 8
|
||||
#define U80211_DRV_RTL8188EU_CAM_CTL0_KEY_ID_MASK 0x03
|
||||
#define U80211_DRV_RTL8188EU_CAM_CTL0_ALGORITHM_SHIFT 2
|
||||
#define U80211_DRV_RTL8188EU_CAM_CTL0_GROUP (1u << 6)
|
||||
#define U80211_DRV_RTL8188EU_CAM_CTL0_VALID (1u << 15)
|
||||
#define U80211_DRV_RTL8188EU_CAM_ALGORITHM_WEP40 1
|
||||
#define U80211_DRV_RTL8188EU_CAM_ALGORITHM_TKIP 2
|
||||
#define U80211_DRV_RTL8188EU_CAM_ALGORITHM_CCMP 4
|
||||
#define U80211_DRV_RTL8188EU_CAM_ALGORITHM_WEP104 5
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_SECCFG 0x0680
|
||||
#define U80211_DRV_RTL8188EU_REG_SECCFG_TXUCKEY_DEF (1u << 0)
|
||||
#define U80211_DRV_RTL8188EU_REG_SECCFG_RXUCKEY_DEF (1u << 1)
|
||||
#define U80211_DRV_RTL8188EU_REG_SECCFG_TXENC_ENABLE (1u << 2)
|
||||
#define U80211_DRV_RTL8188EU_REG_SECCFG_RXENC_ENABLE (1u << 3)
|
||||
#define U80211_DRV_RTL8188EU_REG_SECCFG_TXBCKEY_DEF (1u << 6)
|
||||
#define U80211_DRV_RTL8188EU_REG_SECCFG_RXBCKEY_DEF (1u << 7)
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_RXFLTMAP0 0x06a0
|
||||
#define U80211_DRV_RTL8188EU_REG_RXFLTMAP1 0x06a2
|
||||
#define U80211_DRV_RTL8188EU_REG_RXFLTMAP2 0x06a4
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_FPGA0_RFMOD 0x0800
|
||||
#define U80211_DRV_RTL8188EU_REG_FPGA_RFMOD_40MHZ (1u << 0)
|
||||
#define U80211_DRV_RTL8188EU_REG_FPGA0_RFMOD_CCK_ENABLE (1u << 24)
|
||||
#define U80211_DRV_RTL8188EU_REG_FPGA0_RFMOD_OFDM_ENABLE (1u << 25)
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_HSSI_PARAM1_A 0x0820
|
||||
#define U80211_DRV_RTL8188EU_REG_HSSI_PARAM1_PI (1u << 8)
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_HSSI_PARAM2_A 0x0824
|
||||
#define U80211_DRV_RTL8188EU_REG_HSSI_PARAM2_CCK_HIGH_POWER (1u << 9)
|
||||
#define U80211_DRV_RTL8188EU_REG_HSSI_PARAM2_ADDRESS_LENGTH (1u << 10)
|
||||
#define U80211_DRV_RTL8188EU_REG_HSSI_PARAM2_DATA_LENGTH (1u << 11)
|
||||
#define U80211_DRV_RTL8188EU_REG_HSSI_PARAM2_READ_ADDRESS_MASK 0x7f800000
|
||||
#define U80211_DRV_RTL8188EU_REG_HSSI_PARAM2_READ_ADDRESS_SHIFT 23
|
||||
#define U80211_DRV_RTL8188EU_REG_HSSI_PARAM2_READ_EDGE (1u << 31)
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_LSSI_PARAM_A 0x0840
|
||||
#define U80211_DRV_RTL8188EU_REG_LSSI_PARAM_ADDRESS_SHIFT 20
|
||||
#define U80211_DRV_RTL8188EU_REG_LSSI_PARAM_DATA_MASK 0x000fffff
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_RF_IFACE_OE_A 0x0860
|
||||
#define U80211_DRV_RTL8188EU_REG_RF_IFACE_OE_RF_ENV (1u << 4)
|
||||
#define U80211_DRV_RTL8188EU_REG_RF_IFACE_OE_RF_ENV_ENABLE (1u << 20)
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_TXAGC_B_CCK11_A_CCK2_11 0x086c
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_RF_IFACE_SW_A 0x0870
|
||||
#define U80211_DRV_RTL8188EU_REG_RF_IFACE_SW_RF_ENV (1u << 4)
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_LSSI_READBACK_A 0x08a0
|
||||
#define U80211_DRV_RTL8188EU_REG_HSPI_READBACK_A 0x08b8
|
||||
#define U80211_DRV_RTL8188EU_RF_READBACK_MASK 0x000fffff
|
||||
#define U80211_DRV_RTL8188EU_RF_CHNLBW 0x18
|
||||
#define U80211_DRV_RTL8188EU_RF_CHNLBW_CHANNEL_BW_MASK 0x00000fff
|
||||
#define U80211_DRV_RTL8188EU_RF_CHNLBW_BW20 0x00000c00
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_FPGA1_RFMOD 0x0900
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_OFDM0_AGCCORE1 0x0c50
|
||||
#define U80211_DRV_RTL8188EU_REG_OFDM0_AGCCORE1_LATCH 0x69553422
|
||||
#define U80211_DRV_RTL8188EU_REG_OFDM0_AGCCORE1_FINAL 0x69553420
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_OFDM0_AGCRSSITABLE 0x0c78
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_TXAGC_A_RATE18_06 0x0e00
|
||||
#define U80211_DRV_RTL8188EU_REG_TXAGC_A_RATE54_24 0x0e04
|
||||
#define U80211_DRV_RTL8188EU_REG_TXAGC_A_CCK1 0x0e08
|
||||
#define U80211_DRV_RTL8188EU_REG_TXAGC_A_MCS03 0x0e10
|
||||
#define U80211_DRV_RTL8188EU_REG_TXAGC_A_MCS07 0x0e14
|
||||
#define U80211_DRV_RTL8188EU_REG_TXAGC_A_CCK1_MASK 0x0000ff00
|
||||
|
||||
#define U80211_DRV_RTL8188EU_REG_USB_SPECIAL_OPTION 0xfe55
|
||||
#define U80211_DRV_RTL8188EU_REG_USB_SPECIAL_OPTION_AGG_ENABLE (1u << 3)
|
||||
|
||||
#define U80211_DRV_RTL8188EU_TX_TOTAL_PAGE_NUM 0xa9
|
||||
#define U80211_DRV_RTL8188EU_TX_PAGE_NUM_HI_PQ 0x29
|
||||
#define U80211_DRV_RTL8188EU_TX_PAGE_NUM_LO_PQ 0x1c
|
||||
#define U80211_DRV_RTL8188EU_TX_PAGE_NUM_NORM_PQ 0x1c
|
||||
|
||||
#define U80211_DRV_RTL8188EU_TRXDMA_QUEUE_LOW 1
|
||||
#define U80211_DRV_RTL8188EU_TRXDMA_QUEUE_NORMAL 2
|
||||
#define U80211_DRV_RTL8188EU_TRXDMA_QUEUE_HIGH 3
|
||||
|
||||
#define U80211_DRV_RTL8188EU_RX_SLOT_COUNT 4
|
||||
|
||||
typedef enum {
|
||||
U80211_DRV_RTL8188EU_ACCESS_CATEGORY_VO,
|
||||
U80211_DRV_RTL8188EU_ACCESS_CATEGORY_VI,
|
||||
U80211_DRV_RTL8188EU_ACCESS_CATEGORY_BE,
|
||||
U80211_DRV_RTL8188EU_ACCESS_CATEGORY_BK,
|
||||
} u80211_drv_rtl8188eu_access_category_t;
|
||||
|
||||
typedef struct {
|
||||
uint8_t aifsn;
|
||||
uint8_t ecwmin;
|
||||
uint8_t ecwmax;
|
||||
uint16_t txop;
|
||||
uint8_t slot_time;
|
||||
} u80211_drv_rtl8188eu_edca_params_t;
|
||||
|
||||
typedef struct {
|
||||
uint16_t rtl_id;
|
||||
uint8_t mac_address[U80211_DRV_RTL8188EU_MAC_ADDRESS_LEN];
|
||||
uint8_t cck_tx_power_base_indexes[U80211_DRV_RTL8188EU_CCK_TX_POWER_BASE_INDEX_COUNT];
|
||||
uint8_t ht40_1s_tx_power_base_indexes[U80211_DRV_RTL8188EU_HT40_1S_TX_POWER_BASE_INDEX_COUNT];
|
||||
uint8_t ht20_ofdm_tx_power_diff;
|
||||
uint8_t xtal_k;
|
||||
} u80211_drv_rtl8188eu_efuse_t;
|
||||
|
||||
typedef struct u80211_drv_rtl8188eu u80211_drv_rtl8188eu_t;
|
||||
|
||||
typedef struct {
|
||||
u80211_drv_rtl8188eu_t *rtl8188eu;
|
||||
void *buffer;
|
||||
u80211_drv_transfer_handle_t transfer;
|
||||
} u80211_drv_rtl8188eu_rx_slot_t;
|
||||
|
||||
struct u80211_drv_rtl8188eu {
|
||||
u80211_drv_device_handle_t device;
|
||||
u80211_drv_interface_handle_t interface;
|
||||
u80211_drv_network_device_handle_t network_device;
|
||||
uint8_t rx_endpoint;
|
||||
uint8_t bulk_out_endpoint_count;
|
||||
uint8_t tx_endpoint_high;
|
||||
uint8_t tx_endpoint_normal;
|
||||
uint8_t tx_endpoint_low;
|
||||
bool cck_high_power;
|
||||
uint32_t rf_chnlbw;
|
||||
u80211_drv_rtl8188eu_efuse_t efuse;
|
||||
u80211_drv_rtl8188eu_rx_slot_t rx_slots[U80211_DRV_RTL8188EU_RX_SLOT_COUNT];
|
||||
};
|
||||
|
||||
int u80211_drv_rtl8188eu_efuse_prepare(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_efuse_finish(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_read_efuse(u80211_drv_device_handle_t device, uint8_t efuse_map[U80211_DRV_RTL8188EU_EFUSE_MAP_LEN]);
|
||||
int u80211_drv_rtl8188eu_parse_efuse(const uint8_t efuse_map[U80211_DRV_RTL8188EU_EFUSE_MAP_LEN], u80211_drv_rtl8188eu_efuse_t *result);
|
||||
|
||||
int u80211_drv_rtl8188eu_power_active(u80211_drv_device_handle_t device);
|
||||
|
||||
int u80211_drv_rtl8188eu_mac_enable_infrastructure(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_mac_enable_tx_rx(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_mac_disable_rx_aggregation(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_mac_configure_tx_queues(u80211_drv_device_handle_t device, uint8_t bulk_out_endpoint_count);
|
||||
int u80211_drv_rtl8188eu_mac_configure_rx_fifo_boundary(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_mac_configure_packet_buffer(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_mac_initialize_llt(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_mac_configure_wmac(u80211_drv_rtl8188eu_t *rtl8188eu);
|
||||
int u80211_drv_rtl8188eu_mac_set_edca(u80211_drv_device_handle_t device, u80211_drv_rtl8188eu_access_category_t access_category, u80211_drv_rtl8188eu_edca_params_t params);
|
||||
int u80211_drv_rtl8188eu_mac_configure_timing(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_mac_configure_hardware_offloads(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_mac_load_table(u80211_drv_device_handle_t device);
|
||||
|
||||
int u80211_drv_rtl8188eu_bb_enable(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_bb_enable_datapaths(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_bb_load_table(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_bb_load_agc_table(u80211_drv_device_handle_t device);
|
||||
int u80211_drv_rtl8188eu_bb_apply_efuse_calibration(u80211_drv_rtl8188eu_t *rtl8188eu);
|
||||
|
||||
int u80211_drv_rtl8188eu_rf_write(u80211_drv_device_handle_t device, uint8_t rf_reg, uint32_t value);
|
||||
int u80211_drv_rtl8188eu_rf_read(u80211_drv_device_handle_t device, uint8_t rf_reg, uint32_t *value);
|
||||
int u80211_drv_rtl8188eu_rf_load_table(u80211_drv_device_handle_t device);
|
||||
|
||||
int u80211_drv_rtl8188eu_set_tx_power(u80211_drv_rtl8188eu_t *rtl8188eu, uint8_t channel);
|
||||
int u80211_drv_rtl8188eu_set_channel(u80211_drv_rtl8188eu_t *rtl8188eu, uint8_t channel);
|
||||
int u80211_drv_rtl8188eu_set_key(u80211_drv_rtl8188eu_t *rtl8188eu, const u80211_drv_key_t *key);
|
||||
int u80211_drv_rtl8188eu_del_key(u80211_drv_rtl8188eu_t *rtl8188eu, uint8_t index);
|
||||
int u80211_drv_rtl8188eu_tx_buffer_allocate(size_t size, void **buffer);
|
||||
void u80211_drv_rtl8188eu_tx_buffer_free(void *buffer);
|
||||
int u80211_drv_rtl8188eu_transmit(u80211_drv_rtl8188eu_t *rtl8188eu, void *buffer, size_t size, size_t current_offset, const u80211_drv_transmit_options_t *options);
|
||||
int u80211_drv_rtl8188eu_rx_start(u80211_drv_rtl8188eu_t *rtl8188eu);
|
||||
|
||||
int u80211_drv_rtl8188eu_calibrate(u80211_drv_device_handle_t device);
|
||||
|
||||
int u80211_drv_rtl8188eu_firmware_prepare(u80211_drv_device_handle_t device, const void *firmware_data, size_t firmware_size, const uint8_t **firmware_payload, size_t *firmware_payload_size);
|
||||
int u80211_drv_rtl8188eu_firmware_upload(u80211_drv_device_handle_t device, const uint8_t *firmware_payload, size_t firmware_payload_size);
|
||||
int u80211_drv_rtl8188eu_firmware_start(u80211_drv_device_handle_t device);
|
||||
|
||||
int u80211_drv_rtl8188eu_reg_read8(u80211_drv_device_handle_t device, uint16_t reg, uint8_t *value);
|
||||
int u80211_drv_rtl8188eu_reg_read16(u80211_drv_device_handle_t device, uint16_t reg, uint16_t *value);
|
||||
int u80211_drv_rtl8188eu_reg_read32(u80211_drv_device_handle_t device, uint16_t reg, uint32_t *value);
|
||||
int u80211_drv_rtl8188eu_reg_write8(u80211_drv_device_handle_t device, uint16_t reg, uint8_t value);
|
||||
int u80211_drv_rtl8188eu_reg_write16(u80211_drv_device_handle_t device, uint16_t reg, uint16_t value);
|
||||
int u80211_drv_rtl8188eu_reg_write32(u80211_drv_device_handle_t device, uint16_t reg, uint32_t value);
|
||||
int u80211_drv_rtl8188eu_reg_write_region(u80211_drv_device_handle_t device, uint16_t reg, const void *data, uint16_t size);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,14 @@
|
||||
#ifndef U80211_DRV_STATUS_H
|
||||
#define U80211_DRV_STATUS_H
|
||||
|
||||
#define U80211_DRV_STATUS_SUCCESS 0
|
||||
#define U80211_DRV_STATUS_NO_MATCH 1
|
||||
#define U80211_DRV_STATUS_UNKNOWN_ERROR 2
|
||||
#define U80211_DRV_STATUS_TIMEOUT 3
|
||||
#define U80211_DRV_STATUS_NOT_SUPPORTED 4
|
||||
#define U80211_DRV_STATUS_FAULTY_HARDWARE 5
|
||||
#define U80211_DRV_STATUS_OUT_OF_MEMORY 6
|
||||
#define U80211_DRV_STATUS_INVALID_ARGUMENT 7
|
||||
#define U80211_DRV_STATUS_MALFORMED_PACKET 8
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,9 @@
|
||||
#ifndef U80211_DRV_STRING_H
|
||||
#define U80211_DRV_STRING_H
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
void *u80211_drv_memcpy(void *destination, const void *source, size_t size);
|
||||
void *u80211_drv_memset(void *destination, int value, size_t size);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,25 @@
|
||||
#ifndef U80211_DRV_U80211_DRV_H
|
||||
#define U80211_DRV_U80211_DRV_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <u80211_drv/kernel_interface.h>
|
||||
#include <u80211_drv/status.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// probes a interface to check if there is a matching driver for a specific usb device
|
||||
// return U80211_DRV_STATUS_SUCCESS when there is a match
|
||||
int u80211_drv_probe(u80211_drv_device_handle_t device, u80211_drv_interface_handle_t interface);
|
||||
|
||||
// attaches an interface to a driver
|
||||
// returns U80211_DRV_STATUS_SUCCESS when driver successfully attaches the interface
|
||||
int u80211_drv_attach(u80211_drv_device_handle_t device, u80211_drv_interface_handle_t interface);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,54 @@
|
||||
#ifndef U80211_DRV_UTIL_H
|
||||
#define U80211_DRV_UTIL_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <u80211_drv/string.h>
|
||||
|
||||
static inline uint16_t u80211_drv_host_to_le16(uint16_t value) {
|
||||
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
|
||||
return value;
|
||||
#else
|
||||
return __builtin_bswap16(value);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline uint32_t u80211_drv_host_to_le32(uint32_t value) {
|
||||
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
|
||||
return value;
|
||||
#else
|
||||
return __builtin_bswap32(value);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline uint16_t u80211_drv_le_to_host16(uint16_t value) {
|
||||
return u80211_drv_host_to_le16(value);
|
||||
}
|
||||
|
||||
static inline uint32_t u80211_drv_le_to_host32(uint32_t value) {
|
||||
return u80211_drv_host_to_le32(value);
|
||||
}
|
||||
|
||||
static inline uint16_t u80211_drv_deserialize_le16(const void *source) {
|
||||
uint16_t value;
|
||||
u80211_drv_memcpy(&value, source, sizeof(value));
|
||||
return u80211_drv_le_to_host16(value);
|
||||
}
|
||||
|
||||
static inline uint32_t u80211_drv_deserialize_le32(const void *source) {
|
||||
uint32_t value;
|
||||
u80211_drv_memcpy(&value, source, sizeof(value));
|
||||
return u80211_drv_le_to_host32(value);
|
||||
}
|
||||
|
||||
static inline void u80211_drv_serialize_le16(uint8_t *destination, uint16_t value) {
|
||||
uint16_t little_endian_value = u80211_drv_host_to_le16(value);
|
||||
u80211_drv_memcpy(destination, &little_endian_value, sizeof(little_endian_value));
|
||||
}
|
||||
|
||||
static inline void u80211_drv_serialize_le32(uint8_t *destination, uint32_t value) {
|
||||
uint32_t little_endian_value = u80211_drv_host_to_le32(value);
|
||||
u80211_drv_memcpy(destination, &little_endian_value, sizeof(little_endian_value));
|
||||
}
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user