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https://github.com/Mathewnd/Astral.git
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Matheus
91ec85d8ca
Panics currently lack backtraces, which are a very useful thing to have. Make the profiling backtrace function generic and print backtraces using it.
131 lines
3.1 KiB
C
131 lines
3.1 KiB
C
#include <kernel/init.h>
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#include <string.h>
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#include <arch/cpu.h>
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#include <arch/cpuid.h>
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#include <kernel/prof.h>
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#include <logging.h>
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#ifdef ENABLE_PROFILING
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#define INTEL_TSC_INDEX 2
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#define INTEL_TSC_INDEX_OFFSET (1lu << 34)
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#define INTEL_TSC_FIXED_CTR_CTRL_OFFSET 8
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#define INTEL_TSC_FIXED_CTR_CTRL_ENABLE (1 << (11))
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#define INTEL_PERF_FIXED_CTR_CTRL_USER 1
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#define INTEL_PERF_FIXED_CTR_CTRL_SUPERVISOR 2
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#define TICK_COUNT 3200000
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static int intel_get_max_size(void) {
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cpuid_results_t cpuid_results;
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cpuid(0xa, &cpuid_results);
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return 1 << ((cpuid_results.eax >> 16) & 0xff);
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}
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static int intel_get_version(void) {
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cpuid_results_t cpuid_results;
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cpuid(0xa, &cpuid_results);
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return cpuid_results.eax & 0xff;
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}
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static bool intel_check_tsc_fixed(void) {
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cpuid_results_t cpuid_results;
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cpuid(0xa, &cpuid_results);
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int fixed_count = cpuid_results.edx & 0x1f;
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return fixed_count > INTEL_TSC_INDEX;
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}
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static void reset_intel_pmc(void) {
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// disable PMCs
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wrmsr(MSR_PERF_FIXED_CTR_CTRL, 0);
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// clear overflow
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wrmsr(MSR_PERF_GLOBAL_OVF_CTRL, INTEL_TSC_INDEX_OFFSET);
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// program PMC
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wrmsr(MSR_PERF_FIXED_CTR2, intel_get_max_size() - TICK_COUNT);
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// enable the PMC
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wrmsr(MSR_PERF_FIXED_CTR_CTRL,
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((INTEL_PERF_FIXED_CTR_CTRL_USER | INTEL_PERF_FIXED_CTR_CTRL_SUPERVISOR) << INTEL_TSC_FIXED_CTR_CTRL_OFFSET) |
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INTEL_TSC_FIXED_CTR_CTRL_ENABLE);
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}
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static void init_intel_pmc(void) {
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// check for version 2 PMC
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if (intel_get_version() < 2) {
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__assert(!"Profiling is not supported on Intel CPUs without at least a version 2 PMC. Recompile without profiling.");
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}
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// check for support for the tsc fixed counter
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__assert(intel_check_tsc_fixed());
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// enable fixed PMC
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wrmsr(MSR_PERF_GLOBAL_CTRL, rdmsr(MSR_PERF_GLOBAL_CTRL) | INTEL_TSC_INDEX_OFFSET);
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reset_intel_pmc();
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arch_apic_init_perf();
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}
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static bool backtrace_fn(void *context, void *ip) {
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uint8_t *data = context;
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if (data[0] == 255)
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return false;
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uintptr_t *trace = (uintptr_t *)&data[1];
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trace[data[0]] = (uintptr_t)ip;
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data[0] += 1;
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return true;
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}
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static bool intel_irq(context_t *context) {
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if ((rdmsr(MSR_PERF_GLOBAL_STATUS) & INTEL_TSC_INDEX_OFFSET) == 0)
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return false;
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uint8_t data[1 + sizeof(uintptr_t) * 255];
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data[0] = 0;
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arch_get_backtrace(context, backtrace_fn, data);
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profiling_insert(data[0], data);
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arch_apic_init_perf(); // SDM LVT figure says a PMC irq masks itself, so unmask it
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reset_intel_pmc();
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return true;
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}
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static bool amd_irq(context_t *context) {
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__assert(!"Unimplemented");
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}
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static void init_amd_pmc(void) {
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__assert(!"Unimplemented");
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}
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bool arch_profiling_irq(context_t *context) {
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if (!strcmp(current_cpu()->vendor, "AuthenticAMD"))
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return amd_irq(context);
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else if (!strcmp(current_cpu()->vendor, "GenuineIntel"))
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return intel_irq(context);
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__assert(!"unreachable");
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}
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void arch_profiling_init(void) {
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arch_apic_init_perf();
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if (!strcmp(current_cpu()->vendor, "AuthenticAMD"))
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init_amd_pmc();
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else if (!strcmp(current_cpu()->vendor, "GenuineIntel"))
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init_intel_pmc();
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else
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printf("arch_prof: no PMC for this vendor\n");
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}
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INIT_ROUTINE_DEFINE(arch_profiling, INIT_ROUTINE_FLAGS_NONE, arch_profiling_init, profiling, cpu);
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#endif
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