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https://github.com/Mathewnd/Astral.git
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101 lines
1.3 KiB
NASM
101 lines
1.3 KiB
NASM
section .text
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%assign i 0
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%rep 256
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isr_%+ i:
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; push an error code if the cpu did not
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%if i <> 8 && i <> 10 && i <> 11 && i <> 12 && i <> 13 && i <> 14
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push qword 0
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%endif
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push rbp ; this push is here to free a register
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mov rbp, i
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jmp isr_common
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%assign i i + 1
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%endrep
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isr_common:
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; check if swapgs is needed
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cmp qword [rsp+24], 0x23
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jne .notneeded1
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swapgs
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.notneeded1:
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; push context
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push rsi
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push rdi
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push r15
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push r14
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push r13
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push r12
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push r11
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push r10
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push r9
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push r8
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push rdx
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push rcx
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push rbx
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push rax
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mov rax, ds
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push rax
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mov rax, es
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push rax
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mov rax, fs
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push rax
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mov rax, gs
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push rax
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mov rdi,cr2
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push rdi
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; set up kernel segments
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mov rdi, 0x10
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mov ds, rdi
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mov es, rdi
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; save ctx pointer and interrupt vector number
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mov rdi, rbp ; vec
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mov rsi, rsp ; ctx
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cld
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extern interrupt_isr
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call interrupt_isr
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cli
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; pop context
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add rsp, 24 ; cr2 gs and fs are not popped.
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pop rax
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mov es,rax
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pop rax
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mov ds,rax
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pop rax
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pop rbx
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pop rcx
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pop rdx
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pop r8
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pop r9
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pop r10
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pop r11
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pop r12
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pop r13
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pop r14
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pop r15
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pop rdi
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pop rsi
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pop rbp
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add rsp,8 ; remove error code
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; check if swapgs is needed
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cmp qword [rsp+8], 0x23
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jne .notneeded2
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swapgs
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.notneeded2:
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o64 iret
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section .rodata
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global isr_table
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isr_table:
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%assign i 0
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%rep 256
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dq isr_%+ i
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%assign i i + 1
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%endrep
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