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https://github.com/Mathewnd/Astral.git
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Matheus
325 lines
8.5 KiB
C
325 lines
8.5 KiB
C
#include <arch/mmu.h>
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#include <limine.h>
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#include <kernel/pmm.h>
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#include <string.h>
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#include <logging.h>
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#include <kernel/interrupt.h>
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#include <kernel/vmm.h>
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#include <arch/cpu.h>
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#include <arch/smp.h>
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#define ADDRMASK (uint64_t)0x7ffffffffffff000
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#define PTMASK (uint64_t)0b111111111000000000000
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#define PDMASK (uint64_t)0b111111111000000000000000000000
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#define PDPTMASK (uint64_t)0b111111111000000000000000000000000000000
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#define PML4MASK (uint64_t)0b111111111000000000000000000000000000000000000000
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#define INTERMEDIATE_FLAGS ARCH_MMU_FLAGS_WRITE | ARCH_MMU_FLAGS_READ | ARCH_MMU_FLAGS_USER
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// returns hhdm address of next entry
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static inline uint64_t* next(uint64_t entry) {
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if (entry == 0)
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return NULL;
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return MAKE_HHDM((entry & ADDRMASK));
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}
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#define DEPTH_PDPT 1
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#define DEPTH_PD 2
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#define DEPTH_PT 3
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// returns pointer to the entry
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static uint64_t *get_page(pagetableptr_t top, void *vaddr) {
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uint64_t *pml4 = MAKE_HHDM(top);
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uintptr_t addr = (uintptr_t)vaddr;
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uintptr_t ptoffset = (addr & PTMASK) >> 12;
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uintptr_t pdoffset = (addr & PDMASK) >> 21;
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uintptr_t pdptoffset = (addr & PDPTMASK) >> 30;
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uintptr_t pml4offset = (addr & PML4MASK) >> 39;
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uint64_t *pdpt = next(pml4[pml4offset]);
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if (pdpt == NULL)
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return NULL;
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uint64_t *pd = next(pdpt[pdptoffset]);
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if (pd == NULL)
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return NULL;
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uint64_t *pt = next(pd[pdoffset]);
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if (pt == NULL)
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return NULL;
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return pt + ptoffset;
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}
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// inserts an entry
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static bool add_page(pagetableptr_t top, void *vaddr, uint64_t entry, int depth) {
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uint64_t *pml4 = MAKE_HHDM(top);
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uintptr_t addr = (uintptr_t)vaddr;
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uintptr_t ptoffset = (addr & PTMASK) >> 12;
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uintptr_t pdoffset = (addr & PDMASK) >> 21;
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uintptr_t pdptoffset = (addr & PDPTMASK) >> 30;
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uintptr_t pml4offset = (addr & PML4MASK) >> 39;
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if (depth == DEPTH_PDPT) {
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pml4[pml4offset] = entry;
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return true;
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}
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uint64_t *pdpt = next(pml4[pml4offset]);
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if (pdpt == NULL) {
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pdpt = pmm_allocpage(PMM_SECTION_DEFAULT);
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if (pdpt == NULL)
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return false;
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pml4[pml4offset] = (uint64_t)pdpt | INTERMEDIATE_FLAGS;
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pdpt = MAKE_HHDM(pdpt);
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memset(pdpt, 0, PAGE_SIZE);
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}
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if (depth == DEPTH_PD) {
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pdpt[pdptoffset] = entry;
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return true;
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}
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uint64_t *pd = next(pdpt[pdptoffset]);
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if (pd == NULL) {
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pd = pmm_allocpage(PMM_SECTION_DEFAULT);
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if (pd == NULL)
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return false;
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pdpt[pdptoffset] = (uint64_t)pd | INTERMEDIATE_FLAGS;
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pd = MAKE_HHDM(pd);
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memset(pd, 0, PAGE_SIZE);
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}
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if (depth == DEPTH_PT) {
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pd[pdoffset] = entry;
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return true;
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}
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uint64_t *pt = next(pd[pdoffset]);
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if (pt == NULL) {
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pt = pmm_allocpage(PMM_SECTION_DEFAULT);
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if (pt == NULL)
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return false;
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pd[pdoffset] = (uint64_t)pt | INTERMEDIATE_FLAGS;
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pt = MAKE_HHDM(pt);
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memset(pt, 0, PAGE_SIZE);
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}
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pt[ptoffset] = entry;
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return true;
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}
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static void destroy(uint64_t *table, int depth) {
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for (int i = 0; i < (depth == 3 ? 256 : 512); ++i) {
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void *addr = (void *)((table[i] & ADDRMASK));
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if (addr == NULL)
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continue;
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if (depth > 0)
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destroy(MAKE_HHDM(addr), depth - 1);
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pmm_release(addr);
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}
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}
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void arch_mmu_destroytable(pagetableptr_t table) {
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destroy(MAKE_HHDM(table), 3);
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pmm_release(table);
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}
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bool arch_mmu_map(pagetableptr_t table, void *paddr, void *vaddr, mmuflags_t flags) {
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uint64_t entry = ((uintptr_t)paddr & ADDRMASK) | flags;
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return add_page(table, vaddr, entry, 0);
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}
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void arch_mmu_invalidate(void *vaddr) {
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arch_mmu_tlbshootdown(vaddr);
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asm volatile ("invlpg (%%rax)" : : "a"(vaddr));
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}
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void arch_mmu_unmap(pagetableptr_t table, void *vaddr) {
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uint64_t *entry = get_page(table, vaddr);
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if (entry == NULL)
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return;
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*entry = 0;
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arch_mmu_invalidate(vaddr);
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}
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void arch_mmu_remap(pagetableptr_t table, void *paddr, void *vaddr, mmuflags_t flags) {
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uint64_t *entryptr = get_page(table, vaddr);
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if (entryptr == NULL)
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return;
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uintptr_t addr = paddr == NULL ? (*entryptr & ADDRMASK) : ((uintptr_t)paddr & ADDRMASK);
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*entryptr = addr | flags;
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arch_mmu_invalidate(vaddr);
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}
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void *arch_mmu_getphysical(pagetableptr_t table, void *vaddr) {
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uint64_t *entry = get_page(table, vaddr);
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if (entry == NULL)
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return NULL;
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return (void *)(*entry & ADDRMASK);
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}
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bool arch_mmu_ispresent(pagetableptr_t table, void *vaddr) {
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uint64_t *entry = get_page(table, vaddr);
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return entry == NULL ? false : *entry & ARCH_MMU_FLAGS_READ;
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}
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bool arch_mmu_iswritable(pagetableptr_t table, void *vaddr) {
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uint64_t *entry = get_page(table, vaddr);
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return entry == NULL ? false : *entry & ARCH_MMU_FLAGS_WRITE;
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}
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void arch_mmu_switch(pagetableptr_t table) {
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asm volatile("mov %%rax, %%cr3" : : "a"(table));
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}
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// hhdm pointer to template to be used for new mappings and smp bootup
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static pagetableptr_t template;
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pagetableptr_t arch_mmu_newtable() {
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pagetableptr_t table = pmm_allocpage(PMM_SECTION_DEFAULT);
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if (table == NULL)
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return NULL;
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memcpy(MAKE_HHDM(table), template, PAGE_SIZE);
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return table;
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}
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static void *mmupage = NULL;
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static spinlock_t shootdownlock;
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static int remaining = 0;
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void arch_mmu_tlbipi(isr_t *isr, context_t *context) {
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asm volatile ("invlpg (%%rax)" : : "a"(mmupage));
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__atomic_sub_fetch(&remaining, 1, __ATOMIC_SEQ_CST);
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}
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void arch_mmu_tlbshootdown(void *page) {
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// scheduler not up yet, or there are no other cpus, nothing to do
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if (_cpu()->thread == NULL || arch_smp_cpusawake == 1)
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return;
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if (page >= KERNELSPACE_START ||
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(_cpu()->thread->proc->runningthreadcount > 1 && page >= USERSPACE_START && page < USERSPACE_END)) {
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// shoot down if page is in the kernel space or in a multithreaded userland application
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int oldipl = interrupt_raiseipl(IPL_DPC);
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spinlock_acquire(&shootdownlock);
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mmupage = page;
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remaining = arch_smp_cpusawake - 1;
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arch_smp_sendipi(NULL, &_cpu()->isr[0xfe], ARCH_SMP_IPI_OTHERCPUS);
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while (__atomic_load_n(&remaining, __ATOMIC_SEQ_CST)) CPU_PAUSE();
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spinlock_release(&shootdownlock);
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interrupt_loweripl(oldipl);
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}
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}
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extern void *_text_start;
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extern void *_data_start;
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extern void *_rodata_start;
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extern void *_text_end;
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extern void *_data_end;
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extern void *_rodata_end;
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static void *kerneladdr[6] = {
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&_text_start,
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&_text_end,
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&_data_start,
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&_data_end,
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&_rodata_start,
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&_rodata_end
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};
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static mmuflags_t kernelflags[3] = {
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ARCH_MMU_FLAGS_READ,
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ARCH_MMU_FLAGS_READ | ARCH_MMU_FLAGS_WRITE | ARCH_MMU_FLAGS_NOEXEC,
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ARCH_MMU_FLAGS_READ | ARCH_MMU_FLAGS_NOEXEC
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};
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extern volatile struct limine_memmap_request pmm_liminemap;
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static volatile struct limine_kernel_address_request kaddrreq = {
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.id = LIMINE_KERNEL_ADDRESS_REQUEST,
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.revision = 0
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};
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#define ERROR_PRESENT 1
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#define ERROR_WRITE 2
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#define ERROR_FETCH 16
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static void pfisr(isr_t *self, context_t *ctx) {
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interrupt_set(true);
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int vmmerror = 0;
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if (ctx->error & ERROR_PRESENT)
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vmmerror |= VMM_ACTION_READ;
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if (ctx->error & ERROR_WRITE)
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vmmerror |= VMM_ACTION_WRITE;
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if (ctx->error & ERROR_FETCH)
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vmmerror |= VMM_ACTION_EXEC;
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if (vmm_pagefault((void *)ctx->cr2, ctx->cs != 8, vmmerror) == false) {
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if (ARCH_CONTEXT_ISUSER(ctx))
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signal_signalthread(_cpu()->thread, SIGSEGV, true);
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else
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_panic("Page fault", ctx);
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}
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}
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void arch_mmu_init() {
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template = pmm_allocpage(PMM_SECTION_DEFAULT);
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__assert(template);
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template = MAKE_HHDM(template);
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memset(template, 0, PAGE_SIZE);
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for (int i = 256; i < 512; ++i) {
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uint64_t *entry = pmm_allocpage(PMM_SECTION_DEFAULT);
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__assert(entry);
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memset(MAKE_HHDM(entry), 0, PAGE_SIZE);
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template[i] = (uint64_t)entry | INTERMEDIATE_FLAGS;
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}
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// TODO use 2mb pages
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// populate hhdm
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for (size_t i = 0; i < pmm_liminemap.response->entry_count; ++i) {
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struct limine_memmap_entry *e = pmm_liminemap.response->entries[i];
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for (uint64_t i = 0; i < e->length; i += PAGE_SIZE) {
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uint64_t entry = ((e->base + i) & ADDRMASK) | ARCH_MMU_FLAGS_READ | ARCH_MMU_FLAGS_WRITE | ARCH_MMU_FLAGS_NOEXEC;
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__assert(add_page(FROM_HHDM(template), MAKE_HHDM((void *)(e->base + i)), entry, 0));
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}
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}
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__assert(kaddrreq.response);
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// populate kernel
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for (int i = 0; i < 3; ++i) {
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size_t len = (uintptr_t)kerneladdr[i*2+1] - (uintptr_t)kerneladdr[i*2];
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uintptr_t baseptr = (uintptr_t)kerneladdr[i*2];
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uintptr_t physicalbase = (uintptr_t)kerneladdr[i*2] - kaddrreq.response->virtual_base + kaddrreq.response->physical_base;
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for (uintptr_t off = 0; off < len; off += PAGE_SIZE) {
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uint64_t entry = ((physicalbase + off) & ADDRMASK) | kernelflags[i];
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__assert(add_page(FROM_HHDM(template), (void *)(baseptr + off), entry, 0));
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}
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}
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arch_mmu_apswitch();
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}
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void arch_mmu_apswitch() {
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arch_mmu_switch(FROM_HHDM(template));
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interrupt_register(14, pfisr, NULL, IPL_IGNORE);
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interrupt_register(0xfe, arch_mmu_tlbipi, ARCH_EOI, IPL_IGNORE);
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}
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