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riscv64: move trap code into ke

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Loïc Grégoire
2026-09-27 21:36:23 -04:00
parent ec05f050fb
commit 26084dbb99
4 changed files with 92 additions and 88 deletions
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src/kern/riscv64/int.zig
+16
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@@ -0,0 +1,16 @@
const r = @import("root");
const ke = r.ke;
const std = @import("std");
export fn riscv_trap_handler(cause: usize, pc: usize) callconv(.c) void {
if (cause == ((@as(usize, 1) << 63) | 5)) {
const old = ke.ipl.set_hardware(.Device);
ke.private.timer.clock();
_ = ke.ipl.set_hardware(old);
if (old == .Passive and ke.private.ipl.is_softint_pending(.Dispatch)) {
ke.private.dpc.dispatch();
}
return;
}
std.debug.panic("trap: cause = 0x{x}, pc = 0x{x}, tval = 0x{x}", .{ cause, pc, rv64.read_csr("stval") });
}
src/kern/riscv64/locore.s
+76
View File
@@ -69,3 +69,79 @@ thread_start:
mv a0, s1
mv a1, s2
tail riscv_thread_entry
.section .text
.global riscv_trap
.type riscv_trap, @function
riscv_trap:
addi sp, sp, -272
sd ra, 0(sp)
sd gp, 8(sp)
sd tp, 16(sp)
sd t0, 24(sp)
sd t1, 32(sp)
sd t2, 40(sp)
sd s0, 48(sp)
sd s1, 56(sp)
sd a0, 64(sp)
sd a1, 72(sp)
sd a2, 80(sp)
sd a3, 88(sp)
sd a4, 96(sp)
sd a5, 104(sp)
sd a6, 112(sp)
sd a7, 120(sp)
sd s2, 128(sp)
sd s3, 136(sp)
sd s4, 144(sp)
sd s5, 152(sp)
sd s6, 160(sp)
sd s7, 168(sp)
sd s8, 176(sp)
sd s9, 184(sp)
sd s10, 192(sp)
sd s11, 200(sp)
sd t3, 208(sp)
sd t4, 216(sp)
sd t5, 224(sp)
sd t6, 232(sp)
csrr t0, sepc
sd t0, 240(sp)
csrr a0, scause
mv a1, t0
call riscv_trap_handler
ld t0, 240(sp)
csrw sepc, t0
ld ra, 0(sp)
ld gp, 8(sp)
ld tp, 16(sp)
ld t0, 24(sp)
ld t1, 32(sp)
ld t2, 40(sp)
ld s0, 48(sp)
ld s1, 56(sp)
ld a0, 64(sp)
ld a1, 72(sp)
ld a2, 80(sp)
ld a3, 88(sp)
ld a4, 96(sp)
ld a5, 104(sp)
ld a6, 112(sp)
ld a7, 120(sp)
ld s2, 128(sp)
ld s3, 136(sp)
ld s4, 144(sp)
ld s5, 152(sp)
ld s6, 160(sp)
ld s7, 168(sp)
ld s8, 176(sp)
ld s9, 184(sp)
ld s10, 192(sp)
ld s11, 200(sp)
ld t3, 208(sp)
ld t4, 216(sp)
ld t5, 224(sp)
ld t6, 232(sp)
addi sp, sp, 272
sret
src/platform/riscv64/impl.zig
-14
View File
@@ -34,20 +34,6 @@ pub fn late_init() void {
: .{ .memory = true });
}
export fn riscv_trap_handler(cause: usize, pc: usize) callconv(.c) void {
if (cause == ((@as(usize, 1) << 63) | 5)) {
const old = ke.ipl.set_hardware(.Device);
set_timer(std.math.maxInt(u64));
ke.private.timer.clock();
_ = ke.ipl.set_hardware(old);
if (old == .Passive and ke.private.ipl.is_softint_pending(.Dispatch)) {
ke.private.dpc.dispatch();
}
return;
}
std.debug.panic("trap: cause = 0x{x}, pc = 0x{x}, tval = 0x{x}", .{ cause, pc, rv64.read_csr("stval") });
}
fn set_timer(deadline: u64) void {
asm volatile ("ecall"
:
src/platform/riscv64/trap.s
-74
View File
@@ -1,74 +0,0 @@
.section .text
.global riscv_trap
.type riscv_trap, @function
riscv_trap:
addi sp, sp, -272
sd ra, 0(sp)
sd gp, 8(sp)
sd tp, 16(sp)
sd t0, 24(sp)
sd t1, 32(sp)
sd t2, 40(sp)
sd s0, 48(sp)
sd s1, 56(sp)
sd a0, 64(sp)
sd a1, 72(sp)
sd a2, 80(sp)
sd a3, 88(sp)
sd a4, 96(sp)
sd a5, 104(sp)
sd a6, 112(sp)
sd a7, 120(sp)
sd s2, 128(sp)
sd s3, 136(sp)
sd s4, 144(sp)
sd s5, 152(sp)
sd s6, 160(sp)
sd s7, 168(sp)
sd s8, 176(sp)
sd s9, 184(sp)
sd s10, 192(sp)
sd s11, 200(sp)
sd t3, 208(sp)
sd t4, 216(sp)
sd t5, 224(sp)
sd t6, 232(sp)
csrr t0, sepc
sd t0, 240(sp)
csrr a0, scause
mv a1, t0
call riscv_trap_handler
ld t0, 240(sp)
csrw sepc, t0
ld ra, 0(sp)
ld gp, 8(sp)
ld tp, 16(sp)
ld t0, 24(sp)
ld t1, 32(sp)
ld t2, 40(sp)
ld s0, 48(sp)
ld s1, 56(sp)
ld a0, 64(sp)
ld a1, 72(sp)
ld a2, 80(sp)
ld a3, 88(sp)
ld a4, 96(sp)
ld a5, 104(sp)
ld a6, 112(sp)
ld a7, 120(sp)
ld s2, 128(sp)
ld s3, 136(sp)
ld s4, 144(sp)
ld s5, 152(sp)
ld s6, 160(sp)
ld s7, 168(sp)
ld s8, 176(sp)
ld s9, 184(sp)
ld s10, 192(sp)
ld s11, 200(sp)
ld t3, 208(sp)
ld t4, 216(sp)
ld t5, 224(sp)
ld t6, 232(sp)
addi sp, sp, 272
sret