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https://github.com/rdmsr/zag.git
synced 2026-11-01 15:48:21 +00:00
feat: amd64 interrupts
This commit is contained in:
Loïc Grégoire
@@ -5,6 +5,8 @@ const amd64 = b.arch;
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const std = @import("std");
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pub const early_init = @import("init.zig").early_init;
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pub const Cpu = struct {
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self_ptr: *Cpu,
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percpu_offset: usize,
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@@ -122,15 +124,15 @@ pub inline fn set_hardware_ipl(ipl: ke.Ipl) void {
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}
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pub inline fn enable_interrupts() void {
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amd64.cpu.sti();
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amd64.sti();
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}
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pub inline fn disable_interrupts() bool {
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const rflags = amd64.cpu.rflags();
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const ie = amd64.rflags().interrupt_enable;
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amd64.cpu.cli();
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amd64.cli();
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return rflags & (1 << 9) != 0;
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return ie;
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}
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pub inline fn restore_interrupts(state: bool) void {
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@@ -0,0 +1,37 @@
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const amd64 = @import("arch");
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const int = @import("int.zig");
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const b = @import("base");
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var gdt = extern struct {
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entries: [9]u64 align(1),
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tss: amd64.TssDescriptor align(1),
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}{
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.entries = .{
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0, // null
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0x00009a000000ffff, // code16
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0x000093000000ffff, // data16
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0x00cf9a000000ffff, // code32
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0x00cf93000000ffff, // data32
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0x00af9b000000ffff, // kernel code64
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0x00af93000000ffff, // kernel data64
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0x00aff3000000ffff, // user code64
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0x00affb000000ffff, // user data64
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},
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.tss = undefined,
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};
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extern fn gdt_load(gdtr: *const amd64.Gdtr) callconv(.{ .x86_64_sysv = .{} }) void;
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pub fn early_init() linksection(b.init) void {
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const gdtr: amd64.Gdtr = .{
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.limit = @sizeOf(@TypeOf(gdt)) - 1,
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.base = @intFromPtr(&gdt),
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};
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gdt_load(&gdtr);
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int.init();
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asm volatile ("int3");
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}
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@@ -0,0 +1,73 @@
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const amd64 = @import("arch");
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const std = @import("std");
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const b = @import("base");
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extern const __interrupt_vectors: [256]usize;
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var idt: [256]amd64.IdtEntry align(16) = undefined;
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const exception_msg = [32][]const u8{
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"Divide Error",
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"Debug",
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"Non-Maskable Interrupt",
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"Breakpoint",
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"Overflow",
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"Bound Range Exceeded",
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"Invalid Opcode",
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"Device Not Available",
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"Double Fault",
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"Coprocessor Segment Overrun",
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"Invalid TSS",
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"Segment Not Present",
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"Stack-Segment Fault",
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"General Protection Fault",
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"Page Fault",
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"???",
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"x87 Floating-Point Exception",
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"Alignment Check",
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"Machine Check",
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"SIMD Floating-Point Exception",
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"Virtualization Exception",
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"Control Protection Exception",
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"???",
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"???",
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"???",
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"???",
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"???",
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"???",
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"???",
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"???",
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"???",
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"Security Exception",
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};
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export fn isr_handler_main(frame: *const amd64.IrqFrame) callconv(.{ .x86_64_sysv = .{} }) void {
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if (frame.intno < 32) {
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std.log.info("Unhandled exception: 0x{x} ({s}), err=0x{x}, pc=0x{x}", .{ frame.intno, exception_msg[frame.intno], frame.errcode, frame.rip });
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std.log.info("RAX=0x{x:0>16} RBX=0x{x:0>16} RCX=0x{x:0>16} RDX=0x{x:0>16}", .{ frame.rax, frame.rbx, frame.rcx, frame.rdx });
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std.log.info("RSI=0x{x:0>16} RDI=0x{x:0>16} RBP=0x{x:0>16} RSP=0x{x:0>16}", .{ frame.rsi, frame.rdi, frame.rbp, frame.rsp });
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std.log.info("R8= 0x{x:0>16} R9=0x{x:0>16} R10=0x{x:0>16} R11=0x{x:0>16}", .{ frame.r8, frame.r9, frame.r10, frame.r11 });
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std.log.info("R12=0x{x:0>16} R13=0x{x:0>16} R14=0x{x:0>16} R15=0x{x:0>16}", .{ frame.r12, frame.r13, frame.r14, frame.r15 });
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const cr2 = amd64.read_cr(2);
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const cr3 = amd64.read_cr(3);
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const rflags = amd64.rflags();
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std.log.info("CR2=0x{x:0>16} CR3=0x{x:0>16} RFLAGS={x}", .{ cr2, cr3, @as(u64, @bitCast(rflags)) });
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@panic("Unhandled exception");
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}
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}
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extern fn idt_load(idt_ptr: *const amd64.Idtr) callconv(.{ .x86_64_sysv = .{} }) void;
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pub fn init() linksection(b.init) void {
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const idtr: amd64.Idtr = .{
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.limit = @sizeOf(@TypeOf(idt)) - 1,
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.base = @intFromPtr(&idt),
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};
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for (&idt, 0..256) |*entry, i| {
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entry.* = .init(0x28, 0, .InterruptGate, __interrupt_vectors[i]);
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}
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idt_load(&idtr);
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}
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@@ -0,0 +1,133 @@
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.altmacro
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.code64
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.section .text
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.globl gdt_load
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gdt_load:
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lgdt (%rdi)
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/* Set ss, ds and es to data segment */
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mov $0x30, %ax
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %ss
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/* Save return address */
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pop %rdi
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/* Push CS so the CPU will pop it off with retfq */
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mov $0x28, %rax
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push %rax
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push %rdi
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lretq
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.globl idt_load
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idt_load:
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lidt (%rdi)
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ret
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.macro pushall
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push %rax
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push %rbx
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push %rcx
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push %rdx
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push %rbp
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push %rdi
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push %rsi
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push %r8
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push %r9
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push %r10
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push %r11
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push %r12
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push %r13
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push %r14
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push %r15
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.endm
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.macro popall
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pop %r15
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pop %r14
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pop %r13
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pop %r12
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pop %r11
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pop %r10
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pop %r9
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pop %r8
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pop %rsi
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pop %rdi
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pop %rbp
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pop %rdx
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pop %rcx
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pop %rbx
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pop %rax
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.endm
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.extern isr_handler_main
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isr_handler:
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cld
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pushall
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mov %rsp, %rdi
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call isr_handler_main
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popall
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cli
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add $16, %rsp
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iretq
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.macro INTERRUPT_NOERR num
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.globl isr\num
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isr\num :
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pushq $0
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pushq $\num
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jmp isr_handler
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.endm
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.macro INTERRUPT_ERR num
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.globl isr\num
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isr\num :
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pushq $\num
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jmp isr_handler
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.endm
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INTERRUPT_NOERR 0
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INTERRUPT_NOERR 1
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INTERRUPT_NOERR 2
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INTERRUPT_NOERR 3
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INTERRUPT_NOERR 4
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INTERRUPT_NOERR 5
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INTERRUPT_NOERR 6
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INTERRUPT_NOERR 7
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INTERRUPT_ERR 8
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INTERRUPT_NOERR 9
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INTERRUPT_ERR 10
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INTERRUPT_ERR 11
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INTERRUPT_ERR 12
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INTERRUPT_ERR 13
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INTERRUPT_ERR 14
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INTERRUPT_NOERR 15
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INTERRUPT_NOERR 16
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INTERRUPT_ERR 17
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INTERRUPT_NOERR 18
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INTERRUPT_NOERR 19
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INTERRUPT_NOERR 20
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INTERRUPT_NOERR 21
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INTERRUPT_NOERR 22
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INTERRUPT_NOERR 23
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INTERRUPT_NOERR 24
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INTERRUPT_NOERR 25
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INTERRUPT_NOERR 26
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INTERRUPT_NOERR 27
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INTERRUPT_NOERR 28
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INTERRUPT_NOERR 29
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INTERRUPT_ERR 30
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INTERRUPT_NOERR 31
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.rept 224
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INTERRUPT_NOERR %32+\+
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.endr
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.global __interrupt_vectors
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__interrupt_vectors:
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.rept 256
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.quad isr\()\+
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.endr
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