From a954844eca6eb0a57089de3714c678fbd41ef26c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Lo=C3=AFc=20Gr=C3=A9goire?= <loic@gregoire.dev>
Date: Sun, 19 Jul 2026 11:27:33 -0400
Subject: [PATCH] rtl: add acq barrier

---
 src/rtl/barrier.zig | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/rtl/barrier.zig b/src/rtl/barrier.zig
index 74b5247..19b253c 100644
--- a/src/rtl/barrier.zig
+++ b/src/rtl/barrier.zig
@@ -60,6 +60,22 @@ pub inline fn mb() void {
     }
 }
 
+/// Acquire Barrier (Load/Load - Load/Store)
+pub inline fn acq() void {
+    switch (builtin.cpu.arch) {
+        .x86, .x86_64 => {
+            asm volatile ("" ::: .{ .memory = true });
+        },
+        .aarch64, .arm => {
+            asm volatile ("dmb ishld" ::: .{ .memory = true });
+        },
+        .riscv64, .riscv32 => {
+            asm volatile ("fence r,rw" ::: .{ .memory = true });
+        },
+        else => @compileError("unsupported architecture"),
+    }
+}
+
 /// Copy to dest from src with atomic loads.
 /// Both addresses need to be aligned.
 pub fn atomic_load_memcpy(dest: anytype, src: anytype, comptime ordering: std.builtin.AtomicOrder) void {