mirror of
https://github.com/rdmsr/zag.git
synced 2026-10-27 13:58:20 +00:00
Loïc Grégoire
723 lines
16 KiB
Zig
723 lines
16 KiB
Zig
//! Wrappers over amd64 CPU definitions and CPUID.
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const std = @import("std");
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const assert = std.debug.assert;
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pub const hypervisor = @import("hypervisor.zig");
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pub const name = "amd64";
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pub const Msr = enum(u32) {
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/// IA32_APIC_BASE
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LapicBase = 0x1B,
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X2ApicBase = 0x800,
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/// IA32_FS_BASE
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FsBase = 0xC000_0100,
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/// IA32_GS_BASE
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GsBase = 0xC000_0101,
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/// IA32_KERNEL_GS_BASE
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KernelGsBase = 0xC000_0102,
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/// IA32_EFER
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Efer = 0xC000_0080,
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/// IA32_STAR
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Star = 0xC000_0081,
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/// IA32_LSTAR
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LStar = 0xC000_0082,
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/// IA32_TSC_DEADLINE
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TscDeadline = 0x6E0,
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/// MSR_KVM_SYSTEM_TIME_NEW
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KvmSystemTimeNew = 0x4B564D01,
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_,
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};
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pub const Efer = packed struct(u64) {
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sce: bool,
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reserved0: u7,
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lme: bool,
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reserved1: u1,
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lma: bool,
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nxe: bool,
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svme: bool,
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lmsle: bool,
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ffxsr: bool,
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tce: bool,
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reserved2: u1,
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mcommit: bool,
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interruptible_wb: bool,
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uaie: bool,
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reserved3: u44,
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};
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pub const IrqFrame = extern struct {
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r15: u64,
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r14: u64,
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r13: u64,
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r12: u64,
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r11: u64,
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r10: u64,
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r9: u64,
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r8: u64,
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rsi: u64,
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rdi: u64,
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rbp: u64,
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rdx: u64,
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rcx: u64,
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rbx: u64,
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rax: u64,
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intno: u64,
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errcode: u64,
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rip: u64,
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cs: u64,
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rflags: u64,
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rsp: u64,
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ss: u64,
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};
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pub inline fn outb(port: u16, value: u8) void {
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asm volatile ("outb %[value], %[port]"
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:
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: [value] "{al}" (value),
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[port] "{dx}" (port),
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);
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}
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pub inline fn outw(port: u16, value: u16) void {
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asm volatile ("outw %[value], %[port]"
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:
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: [value] "{ax}" (value),
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[port] "{dx}" (port),
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);
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}
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pub inline fn outl(port: u16, value: u32) void {
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asm volatile ("outl %[value], %[port]"
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:
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: [value] "{eax}" (value),
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[port] "{dx}" (port),
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);
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}
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pub inline fn inb(port: u16) u8 {
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return asm volatile ("inb %[port], %[ret]"
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: [ret] "={al}" (-> u8),
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: [port] "{dx}" (port),
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);
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}
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pub inline fn inw(port: u16) u16 {
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return asm volatile ("inw %[port], %[ret]"
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: [ret] "={ax}" (-> u16),
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: [port] "{dx}" (port),
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);
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}
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pub inline fn inl(port: u16) u32 {
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return asm volatile ("inl %[port], %[ret]"
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: [ret] "={eax}" (-> u32),
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: [port] "{dx}" (port),
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);
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}
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pub inline fn rdmsr(msr: u32) u64 {
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var low: u32 = undefined;
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var high: u32 = undefined;
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asm volatile ("rdmsr"
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: [low] "={eax}" (low),
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[high] "={edx}" (high),
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: [msr] "{ecx}" (msr),
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);
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return @as(u64, high) << 32 | low;
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}
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pub inline fn wrmsr(msr: u32, value: u64) void {
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asm volatile ("wrmsr"
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:
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: [low] "{eax}" (@as(u32, @truncate(value))),
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[high] "{edx}" (@as(u32, @truncate(value >> 32))),
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[msr] "{ecx}" (msr),
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);
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}
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pub inline fn read_msr(comptime msr: Msr) u64 {
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return rdmsr(@backingInt(msr));
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}
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pub inline fn write_msr(comptime msr: Msr, value: u64) void {
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wrmsr(@backingInt(msr), value);
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}
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pub inline fn rdgsbase() usize {
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return asm volatile ("rdgsbase %[ret]"
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: [ret] "=r" (-> usize),
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);
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}
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pub inline fn invlpg(addr: u64) void {
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asm volatile ("invlpg (%[addr])"
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:
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: [addr] "r" (addr),
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: .{ .memory = true });
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}
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pub inline fn sti() void {
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asm volatile ("sti");
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}
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pub inline fn cli() void {
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asm volatile ("cli");
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}
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pub inline fn hlt() void {
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asm volatile ("hlt");
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}
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pub fn pio_read(comptime T: type, port: u16) T {
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if (@sizeOf(T) == 1) {
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return inb(port);
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} else if (@sizeOf(T) == 2) {
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return inw(port);
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} else if (@sizeOf(T) == 4) {
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return inl(port);
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} else {
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@compileError("unsupported pio read size");
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}
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}
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pub fn pio_write(comptime T: type, port: u16, value: T) void {
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if (@sizeOf(T) == 1) {
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outb(port, @as(u8, value));
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} else if (@sizeOf(T) == 2) {
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outw(port, @as(u16, value));
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} else if (@sizeOf(T) == 4) {
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outl(port, @as(u32, value));
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} else {
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@compileError("unsupported pio write size");
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}
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}
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pub const RFlags = packed struct(u64) {
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carry: bool,
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reserved0: u1,
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parity: bool,
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reserved1: u1,
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auxiliary: bool,
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reserved2: u1,
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zero: bool,
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sign: bool,
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trap: bool,
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interrupt_enable: bool,
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direction: bool,
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overflow: bool,
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iopl: u2,
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nested_task: bool,
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reserved3: u1,
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resume_: bool,
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virtual_8086_mode: bool,
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alignment_check: bool,
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virtual_interrupt: bool,
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virtual_interrupt_pending: bool,
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id: bool,
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reserved4: u42,
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};
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pub inline fn rflags() RFlags {
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var flags: u64 = undefined;
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asm volatile ("pushfq; pop %[flags]"
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: [flags] "=r" (flags),
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);
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return @bitCast(flags);
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}
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pub inline fn rdtsc() u64 {
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var low: u32 = undefined;
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var high: u32 = undefined;
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asm volatile ("rdtsc"
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: [low] "={eax}" (low),
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[high] "={edx}" (high),
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);
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return @as(u64, high) << 32 | low;
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}
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pub const Cr0 = packed struct(u64) {
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pe: bool,
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mp: bool,
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em: bool,
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ts: bool,
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et: bool,
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ne: bool,
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reserved0: u10,
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wp: bool,
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reserved1: u1,
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am: bool,
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reserved2: u10,
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nw: bool,
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cd: bool,
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pg: bool,
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reserved3: u32,
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};
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comptime {
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_ = Cr0;
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_ = Cr4;
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}
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pub const Cr4 = packed struct(u64) {
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vme: bool,
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pvi: bool,
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tsd: bool,
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de: bool,
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pse: bool,
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pae: bool,
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mce: bool,
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pge: bool,
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pce: bool,
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osfxsr: bool,
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osxmmexcpt: bool,
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umip: bool,
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la57: bool,
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reserved0: u3,
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fsgsbase: bool,
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pcide: bool,
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osxsave: bool,
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reserved1: u1,
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smep: bool,
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smap: bool,
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pke: bool,
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cet: bool,
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reserved2: u40,
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};
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pub inline fn read_cr(comptime n: u8) u64 {
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comptime assert(n != 1);
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return asm volatile (std.fmt.comptimePrint("mov %%cr{}, %[ret]", .{n})
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: [ret] "=r" (-> u64),
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);
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}
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pub inline fn write_cr(comptime n: u8, value: u64) void {
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comptime assert(n != 1);
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asm volatile (std.fmt.comptimePrint("mov %[value], %%cr{}", .{n})
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:
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: [value] "r" (value),
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);
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}
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pub const CpuidResult = struct { eax: u32, ebx: u32, ecx: u32, edx: u32 };
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pub inline fn cpuid(leaf: u32, subleaf: u32) CpuidResult {
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var eax: u32 = undefined;
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var ebx: u32 = undefined;
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var ecx: u32 = undefined;
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var edx: u32 = undefined;
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asm volatile ("cpuid"
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: [eax] "={eax}" (eax),
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[ebx] "={ebx}" (ebx),
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[ecx] "={ecx}" (ecx),
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[edx] "={edx}" (edx),
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: [leaf] "{eax}" (leaf),
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[subleaf] "{ecx}" (subleaf),
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);
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return .{ .eax = eax, .ebx = ebx, .ecx = ecx, .edx = edx };
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}
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pub const CpuidRequest = union(enum) {
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VendorInfo,
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FeatureInfo,
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ExtendedInfo,
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HighestExtendedFunction,
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ExtendedFeatures: ExtendedFeaturesSubLeaf,
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BrandString: BrandStringPart,
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PowerManagementInfo,
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HypervisorId,
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pub const ExtendedFeaturesSubLeaf = enum(u32) {
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First = 0,
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Second = 1,
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Third = 3,
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};
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pub const BrandStringPart = enum(u32) {
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Part0 = 0x80000002,
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Part1 = 0x80000003,
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Part2 = 0x80000004,
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};
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pub fn execute(self: CpuidRequest) CpuidResult {
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const leaf, const subleaf = switch (self) {
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.VendorInfo => .{ 0x0, 0 },
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.FeatureInfo => .{ 0x1, 0 },
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.HighestExtendedFunction => .{ 0x80000000, 0 },
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.ExtendedInfo => .{ 0x80000001, 0 },
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.PowerManagementInfo => .{ 0x80000007, 0 },
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.ExtendedFeatures => |s| .{ 0x7, @backingInt(s) },
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.BrandString => |p| .{ @backingInt(p), 0 },
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.HypervisorId => .{ 0x40000000, 0 },
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};
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return cpuid(leaf, subleaf);
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}
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};
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const FeatureInfoEcx = packed struct(u32) {
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sse3: bool,
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pclmul: bool,
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dtes64: bool,
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monitor: bool,
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ds_cpl: bool,
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vmx: bool,
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smx: bool,
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est: bool,
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tm2: bool,
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ssse3: bool,
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cnxt_id: bool,
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sdbg: bool,
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fma: bool,
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cx16: bool,
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xtpr: bool,
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pdcm: bool,
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reserved0: u1,
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pcid: bool,
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dca: bool,
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sse4_1: bool,
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sse4_2: bool,
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x2apic: bool,
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movbe: bool,
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popcnt: bool,
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tsc_deadline: bool,
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aes: bool,
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xsave: bool,
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osxsave: bool,
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avx: bool,
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f16c: bool,
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rdrand: bool,
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hypervisor: bool,
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};
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const FeatureInfoEdx = packed struct(u32) {
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fpu: bool,
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vme: bool,
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de: bool,
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pse: bool,
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tsc: bool,
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msr: bool,
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pae: bool,
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mce: bool,
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cx8: bool,
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apic: bool,
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reserved0: u1,
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sep: bool,
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mtrr: bool,
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pge: bool,
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mca: bool,
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cmov: bool,
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pat: bool,
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pse36: bool,
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psn: bool,
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clfsh: bool,
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reserved1: u1,
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ds: bool,
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acpi: bool,
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mmx: bool,
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fxsave: bool,
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sse: bool,
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sse2: bool,
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reserved2: u5,
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};
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const ExtendedFeaturesEcx = packed struct(u32) {
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reserved0: u2,
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umip: bool,
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reserved1: u13,
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la57: bool,
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reserved2: u5,
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rdpid: bool,
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reserved3: u9,
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};
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const ExtendedFeaturesEbx = packed struct(u32) {
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reserved0: u7,
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smep: bool,
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reserved1: u12,
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smap: bool,
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reserved2: u11,
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};
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const ExtendedProcessorInfoEdx = packed struct(u32) {
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fpu: bool,
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vme: bool,
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de: bool,
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pse: bool,
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tsc: bool,
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msr: bool,
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pae: bool,
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mce: bool,
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cx8: bool,
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apic: bool,
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reserved0: u1,
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syscall_sysret: bool,
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mtrr: bool,
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pge: bool,
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mca: bool,
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cmov: bool,
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pat: bool,
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pse36: bool,
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reserved1: u1,
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mp: bool,
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nx: bool,
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reserved2: u5,
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pdpe1gb: bool,
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rdtscp: bool,
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reserved3: u1,
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lm: bool,
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_3dnowext: bool,
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_3dnow: bool,
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};
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const PowerManagementInfoEdx = packed struct(u32) {
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reserved0: u8,
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invtsc: bool,
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reserved1: u23,
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};
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fn assert_bit(
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comptime T: type,
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comptime field_name: []const u8,
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comptime expected_bit: u5,
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) void {
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var v: T = @bitCast(@as(u32, 0));
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@field(v, field_name) = true;
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const raw: u32 = @bitCast(v);
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const want = (@as(u32, 1) << expected_bit);
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if (raw != want) @compileError("bit mismatch for field " ++ field_name);
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}
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comptime {
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assert_bit(FeatureInfoEcx, "pcid", 17);
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assert_bit(FeatureInfoEcx, "x2apic", 21);
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assert_bit(FeatureInfoEcx, "tsc_deadline", 24);
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assert_bit(FeatureInfoEcx, "xsave", 26);
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assert_bit(ExtendedFeaturesEcx, "la57", 16);
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assert_bit(ExtendedProcessorInfoEdx, "nx", 20);
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assert_bit(ExtendedProcessorInfoEdx, "pdpe1gb", 26);
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assert_bit(PowerManagementInfoEdx, "invtsc", 8);
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assert_bit(FeatureInfoEdx, "fxsave", 24);
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assert_bit(ExtendedFeaturesEbx, "smap", 20);
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assert_bit(ExtendedFeaturesEbx, "smep", 7);
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}
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pub const CpuVendor = enum {
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Intel,
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Amd,
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Hygon,
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Unknown,
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};
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const known_vendors = [_]struct {
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string: *const [12:0]u8,
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vendor: CpuVendor,
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}{
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.{ .string = "GenuineIntel", .vendor = .Intel },
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.{ .string = "AuthenticAMD", .vendor = .Amd },
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.{ .string = "HygonGenuine", .vendor = .Hygon },
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};
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pub const CpuFeatures = struct {
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x2apic: bool = false,
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five_level_paging: bool = false,
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gib_pages: bool = false,
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tsc_deadline: bool = false,
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fxsave: bool = false,
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xsave: bool = false,
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invariant_tsc: bool = false,
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nx: bool = false,
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pcid: bool = false,
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smap: bool = false,
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smep: bool = false,
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pge: bool = false,
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syscall: bool = false,
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umip: bool = false,
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vendor: CpuVendor = undefined,
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family: u8 = 0,
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brand_string: [48]u8 = undefined,
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};
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|
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pub const HypervisorVendor = enum(u32) {
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Unknown = 0,
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KVM = 1,
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};
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|
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pub const HypervisorInfo = struct {
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brand_string: [12]u8,
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vendor: HypervisorVendor,
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highest_function: u32,
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};
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|
|
pub var cpu_features: CpuFeatures = undefined;
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|
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fn detect_vendor(string: [12]u8) CpuVendor {
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|
for (known_vendors) |v| {
|
|
if (std.mem.eql(u8, string[0..], v.string[0..])) {
|
|
return v.vendor;
|
|
}
|
|
}
|
|
return .Unknown;
|
|
}
|
|
|
|
pub fn detect_cpu_features() void {
|
|
const vendor_info = CpuidRequest.execute(.VendorInfo);
|
|
const max_ext = CpuidRequest.execute(.HighestExtendedFunction).eax;
|
|
const max_basic = vendor_info.eax;
|
|
|
|
var hypervisor_flag = false;
|
|
var vendor_string: [12]u8 = undefined;
|
|
|
|
cpu_features = .{};
|
|
|
|
std.mem.writeInt(u32, vendor_string[0..4], vendor_info.ebx, .little);
|
|
std.mem.writeInt(u32, vendor_string[4..8], vendor_info.edx, .little);
|
|
std.mem.writeInt(u32, vendor_string[8..12], vendor_info.ecx, .little);
|
|
|
|
cpu_features.vendor = detect_vendor(vendor_string);
|
|
|
|
if (max_basic >= 0x1) {
|
|
const r = CpuidRequest.execute(.FeatureInfo);
|
|
const ecx: FeatureInfoEcx = @bitCast(r.ecx);
|
|
const edx: FeatureInfoEdx = @bitCast(r.edx);
|
|
|
|
cpu_features.x2apic = ecx.x2apic;
|
|
cpu_features.tsc_deadline = ecx.tsc_deadline;
|
|
cpu_features.xsave = ecx.xsave;
|
|
cpu_features.pcid = ecx.pcid;
|
|
cpu_features.fxsave = edx.fxsave;
|
|
cpu_features.pge = edx.pge;
|
|
|
|
hypervisor_flag = ecx.hypervisor;
|
|
|
|
const sig = r.eax;
|
|
var family: u8 = @truncate((sig >> 8) & 0xf);
|
|
|
|
if (family == 0xf) {
|
|
family +%= @truncate((sig >> 20) & 0xff);
|
|
}
|
|
|
|
cpu_features.family = family;
|
|
}
|
|
|
|
if (max_basic >= 0x7) {
|
|
const r = CpuidRequest.execute(.{ .ExtendedFeatures = .First });
|
|
const ecx: ExtendedFeaturesEcx = @bitCast(r.ecx);
|
|
const ebx: ExtendedFeaturesEbx = @bitCast(r.ebx);
|
|
cpu_features.smap = ebx.smap;
|
|
cpu_features.smep = ebx.smep;
|
|
cpu_features.five_level_paging = ecx.la57;
|
|
cpu_features.umip = ecx.umip;
|
|
}
|
|
|
|
if (max_ext >= 0x80000001) {
|
|
const r = CpuidRequest.execute(.ExtendedInfo);
|
|
const edx: ExtendedProcessorInfoEdx = @bitCast(r.edx);
|
|
cpu_features.gib_pages = edx.pdpe1gb;
|
|
cpu_features.nx = edx.nx;
|
|
cpu_features.syscall = edx.syscall_sysret;
|
|
}
|
|
|
|
if (max_ext >= 0x80000004) {
|
|
const parts = [_]CpuidResult{
|
|
CpuidRequest.execute(.{ .BrandString = .Part0 }),
|
|
CpuidRequest.execute(.{ .BrandString = .Part1 }),
|
|
CpuidRequest.execute(.{ .BrandString = .Part2 }),
|
|
};
|
|
|
|
var off: usize = 0;
|
|
const brand_string = &cpu_features.brand_string;
|
|
|
|
for (parts) |p| {
|
|
for ([_]u32{ p.eax, p.ebx, p.ecx, p.edx }) |reg| {
|
|
const dst: *[4]u8 = @ptrCast(brand_string[off..].ptr);
|
|
std.mem.writeInt(u32, dst, reg, .little);
|
|
off += 4;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (max_ext >= 0x80000007) {
|
|
const r = CpuidRequest.execute(.PowerManagementInfo);
|
|
const edx: PowerManagementInfoEdx = @bitCast(r.edx);
|
|
cpu_features.invariant_tsc = edx.invtsc;
|
|
}
|
|
|
|
if (hypervisor_flag) {
|
|
hypervisor.detect();
|
|
}
|
|
}
|
|
|
|
pub const TssDescriptor = extern struct {
|
|
length: u16 align(1),
|
|
base_low: u16 align(1),
|
|
base_mid: u8 align(1),
|
|
access: u8 align(1),
|
|
flags_limit_high: u8 align(1),
|
|
base_high: u8 align(1),
|
|
base_upper: u32 align(1),
|
|
reserved: u32 align(1),
|
|
};
|
|
|
|
pub const Tss = extern struct {
|
|
reserved1: u32 align(1),
|
|
rsp: [3]usize align(1),
|
|
reserved2: u64 align(1),
|
|
ist: [7]usize align(1),
|
|
reserved3: u64 align(1),
|
|
reserved4: u16 align(1),
|
|
iopb: u16 align(1),
|
|
};
|
|
|
|
pub const Gdtr = extern struct {
|
|
limit: u16 align(1),
|
|
base: usize align(1),
|
|
};
|
|
|
|
pub const Idtr = extern struct {
|
|
limit: u16 align(1),
|
|
base: usize align(1),
|
|
};
|
|
|
|
pub fn sidtr() Idtr {
|
|
var idtr: Idtr = undefined;
|
|
asm volatile ("sidt (%[p])"
|
|
:
|
|
: [p] "r" (&idtr),
|
|
: .{ .memory = true });
|
|
return idtr;
|
|
}
|
|
|
|
pub const IdtEntry = extern struct {
|
|
offset_low: u16 align(1),
|
|
selector: u16 align(1),
|
|
ist: u8 align(1),
|
|
type_attr: u8 align(1),
|
|
offset_mid: u16 align(1),
|
|
offset_high: u32 align(1),
|
|
reserved: u32 align(1),
|
|
|
|
pub const Attr = enum(u8) {
|
|
InterruptGate = 0x8E,
|
|
TrapGate = 0x8F,
|
|
};
|
|
|
|
pub fn init(cs: u16, ist: u8, attr: Attr, offset: usize) @This() {
|
|
return .{
|
|
.offset_low = @truncate(offset),
|
|
.selector = cs,
|
|
.ist = ist,
|
|
.type_attr = @backingInt(attr),
|
|
.offset_mid = @truncate(offset >> 16),
|
|
.offset_high = @truncate(offset >> 32),
|
|
.reserved = 0,
|
|
};
|
|
}
|
|
};
|
|
|
|
pub const BootInfo = struct {
|
|
cpu_features: CpuFeatures,
|
|
hypervisor_info: ?hypervisor.Info,
|
|
};
|