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convert macros to constexpr

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This commit is contained in:
Marvin
2026-10-15 21:44:10 +02:00
parent 7748a1dac8
commit c62a908735
4 changed files with 246 additions and 216 deletions
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arch/x86_64/include/x86_64/defs.h
+240 -210
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@@ -1,225 +1,255 @@
#pragma once
#define CPUID_1C_SSE3 (1 << 0)
#define CPUID_1C_PCLMUL (1 << 1)
#define CPUID_1C_DTES64 (1 << 2)
#define CPUID_1C_MONITOR (1 << 3)
#define CPUID_1C_DS_CPL (1 << 4)
#define CPUID_1C_VMX (1 << 5)
#define CPUID_1C_SMX (1 << 6)
#define CPUID_1C_EST (1 << 7)
#define CPUID_1C_TM2 (1 << 8)
#define CPUID_1C_SSSE3 (1 << 9)
#define CPUID_1C_CID (1 << 10)
#define CPUID_1C_SDBG (1 << 11)
#define CPUID_1C_FMA (1 << 12)
#define CPUID_1C_CX16 (1 << 13)
#define CPUID_1C_XTPR (1 << 14)
#define CPUID_1C_PDCM (1 << 15)
#define CPUID_1C_PCID (1 << 17)
#define CPUID_1C_DCA (1 << 18)
#define CPUID_1C_SSE4_1 (1 << 19)
#define CPUID_1C_SSE4_2 (1 << 20)
#define CPUID_1C_X2APIC (1 << 21)
#define CPUID_1C_MOVBE (1 << 22)
#define CPUID_1C_POPCNT (1 << 23)
#define CPUID_1C_TSC (1 << 24)
#define CPUID_1C_AES (1 << 25)
#define CPUID_1C_XSAVE (1 << 26)
#define CPUID_1C_OSXSAVE (1 << 27)
#define CPUID_1C_AVX (1 << 28)
#define CPUID_1C_F16C (1 << 29)
#define CPUID_1C_RDRAND (1 << 30)
#define CPUID_1C_HYPERVISOR (1 << 31)
#include <stdint.h>
#define CPUID_1D_FPU (1 << 0)
#define CPUID_1D_VME (1 << 1)
#define CPUID_1D_DE (1 << 2)
#define CPUID_1D_PSE (1 << 3)
#define CPUID_1D_TSC (1 << 4)
#define CPUID_1D_MSR (1 << 5)
#define CPUID_1D_PAE (1 << 6)
#define CPUID_1D_MCE (1 << 7)
#define CPUID_1D_CX8 (1 << 8)
#define CPUID_1D_APIC (1 << 9)
#define CPUID_1D_SEP (1 << 11)
#define CPUID_1D_MTRR (1 << 12)
#define CPUID_1D_PGE (1 << 13)
#define CPUID_1D_MCA (1 << 14)
#define CPUID_1D_CMOV (1 << 15)
#define CPUID_1D_PAT (1 << 16)
#define CPUID_1D_PSE36 (1 << 17)
#define CPUID_1D_PSN (1 << 18)
#define CPUID_1D_CLFLUSH (1 << 19)
#define CPUID_1D_DS (1 << 21)
#define CPUID_1D_ACPI (1 << 22)
#define CPUID_1D_MMX (1 << 23)
#define CPUID_1D_FXSR (1 << 24)
#define CPUID_1D_SSE (1 << 25)
#define CPUID_1D_SSE2 (1 << 26)
#define CPUID_1D_SS (1 << 27)
#define CPUID_1D_HTT (1 << 28)
#define CPUID_1D_TM (1 << 29)
#define CPUID_1D_IA64 (1 << 30)
#define CPUID_1D_PBE (1 << 31)
enum : uint32_t {
CPUID_1C_SSE3 = 1u << 0,
CPUID_1C_PCLMUL = 1u << 1,
CPUID_1C_DTES64 = 1u << 2,
CPUID_1C_MONITOR = 1u << 3,
CPUID_1C_DS_CPL = 1u << 4,
CPUID_1C_VMX = 1u << 5,
CPUID_1C_SMX = 1u << 6,
CPUID_1C_EST = 1u << 7,
CPUID_1C_TM2 = 1u << 8,
CPUID_1C_SSSE3 = 1u << 9,
CPUID_1C_CID = 1u << 10,
CPUID_1C_SDBG = 1u << 11,
CPUID_1C_FMA = 1u << 12,
CPUID_1C_CX16 = 1u << 13,
CPUID_1C_XTPR = 1u << 14,
CPUID_1C_PDCM = 1u << 15,
CPUID_1C_PCID = 1u << 17,
CPUID_1C_DCA = 1u << 18,
CPUID_1C_SSE4_1 = 1u << 19,
CPUID_1C_SSE4_2 = 1u << 20,
CPUID_1C_X2APIC = 1u << 21,
CPUID_1C_MOVBE = 1u << 22,
CPUID_1C_POPCNT = 1u << 23,
CPUID_1C_TSC = 1u << 24,
CPUID_1C_AES = 1u << 25,
CPUID_1C_XSAVE = 1u << 26,
CPUID_1C_OSXSAVE = 1u << 27,
CPUID_1C_AVX = 1u << 28,
CPUID_1C_F16C = 1u << 29,
CPUID_1C_RDRAND = 1u << 30,
CPUID_1C_HYPERVISOR = 1u << 31,
};
#define CPUID_7B_FSGSBASE (1 << 0)
#define CPUID_7B_SGX (1 << 2)
#define CPUID_7B_BMI (1 << 3)
#define CPUID_7B_HLE (1 << 4)
#define CPUID_7B_AVX2 (1 << 5)
#define CPUID_7B_SMEP (1 << 7)
#define CPUID_7B_BMI2 (1 << 8)
#define CPUID_7B_RTM (1 << 11)
#define CPUID_7B_AVX512F (1 << 16)
#define CPUID_7B_AVX512DQ (1 << 17)
#define CPUID_7B_RDSEED (1 << 18)
#define CPUID_7B_ADX (1 << 19)
#define CPUID_7B_SMAP (1 << 20)
#define CPUID_7B_AVX512IFMA (1 << 21)
#define CPUID_7B_CLFLUSHOPT (1 << 23)
#define CPUID_7B_CLWB (1 << 24)
#define CPUID_7B_AVX512CD (1 << 28)
#define CPUID_7B_SHA (1 << 29)
#define CPUID_7B_AVX512BW (1 << 30)
#define CPUID_7B_AVX512VL (1 << 31)
enum : uint32_t {
CPUID_1D_FPU = 1u << 0,
CPUID_1D_VME = 1u << 1,
CPUID_1D_DE = 1u << 2,
CPUID_1D_PSE = 1u << 3,
CPUID_1D_TSC = 1u << 4,
CPUID_1D_MSR = 1u << 5,
CPUID_1D_PAE = 1u << 6,
CPUID_1D_MCE = 1u << 7,
CPUID_1D_CX8 = 1u << 8,
CPUID_1D_APIC = 1u << 9,
CPUID_1D_SEP = 1u << 11,
CPUID_1D_MTRR = 1u << 12,
CPUID_1D_PGE = 1u << 13,
CPUID_1D_MCA = 1u << 14,
CPUID_1D_CMOV = 1u << 15,
CPUID_1D_PAT = 1u << 16,
CPUID_1D_PSE36 = 1u << 17,
CPUID_1D_PSN = 1u << 18,
CPUID_1D_CLFLUSH = 1u << 19,
CPUID_1D_DS = 1u << 21,
CPUID_1D_ACPI = 1u << 22,
CPUID_1D_MMX = 1u << 23,
CPUID_1D_FXSR = 1u << 24,
CPUID_1D_SSE = 1u << 25,
CPUID_1D_SSE2 = 1u << 26,
CPUID_1D_SS = 1u << 27,
CPUID_1D_HTT = 1u << 28,
CPUID_1D_TM = 1u << 29,
CPUID_1D_IA64 = 1u << 30,
CPUID_1D_PBE = 1u << 31,
};
#define CPUID_7C_AVX512VBMI (1 << 1)
#define CPUID_7C_UMIP (1 << 2)
#define CPUID_7C_PKU (1 << 3)
#define CPUID_7C_OSPKE (1 << 4)
#define CPUID_7C_WAITPKG (1 << 5)
#define CPUID_7C_AVX512VBMI2 (1 << 6)
#define CPUID_7C_SHSTK (1 << 7)
#define CPUID_7C_GFNI (1 << 8)
#define CPUID_7C_VAES (1 << 9)
#define CPUID_7C_VPCLMULQDQ (1 << 10)
#define CPUID_7C_AVX512VNNI (1 << 11)
#define CPUID_7C_AVX512BITALG (1 << 12)
#define CPUID_7C_TME_EN (1 << 13)
#define CPUID_7C_AVX512VPOPCNTDQ (1 << 14)
#define CPUID_7C_RDPID (1 << 22)
#define CPUID_7C_KL (1 << 23)
#define CPUID_7C_CLDEMOTE (1 << 25)
#define CPUID_7C_MOVDIRI (1 << 27)
#define CPUID_7C_MOVDIR64B (1 << 28)
#define CPUID_7C_ENQCMD (1 << 29)
enum : uint32_t {
CPUID_7B_FSGSBASE = 1u << 0,
CPUID_7B_SGX = 1u << 2,
CPUID_7B_BMI = 1u << 3,
CPUID_7B_HLE = 1u << 4,
CPUID_7B_AVX2 = 1u << 5,
CPUID_7B_SMEP = 1u << 7,
CPUID_7B_BMI2 = 1u << 8,
CPUID_7B_RTM = 1u << 11,
CPUID_7B_AVX512F = 1u << 16,
CPUID_7B_AVX512DQ = 1u << 17,
CPUID_7B_RDSEED = 1u << 18,
CPUID_7B_ADX = 1u << 19,
CPUID_7B_SMAP = 1u << 20,
CPUID_7B_AVX512IFMA = 1u << 21,
CPUID_7B_CLFLUSHOPT = 1u << 23,
CPUID_7B_CLWB = 1u << 24,
CPUID_7B_AVX512CD = 1u << 28,
CPUID_7B_SHA = 1u << 29,
CPUID_7B_AVX512BW = 1u << 30,
CPUID_7B_AVX512VL = 1u << 31,
};
#define CPUID_7D_UINTR (1 << 5)
#define CPUID_7D_AVX512VP2INTERSECT (1 << 8)
#define CPUID_7D_SERIALIZE (1 << 14)
#define CPUID_7D_TSXLDTRK (1 << 16)
#define CPUID_7D_PCONFIG (1 << 18)
#define CPUID_7D_IBT (1 << 20)
#define CPUID_7D_AMX_BF16 (1 << 22)
#define CPUID_7D_AVX512FP16 (1 << 23)
#define CPUID_7D_AMX_TILE (1 << 24)
#define CPUID_7D_AMX_INT8 (1 << 25)
enum : uint32_t {
CPUID_7C_AVX512VBMI = 1u << 1,
CPUID_7C_UMIP = 1u << 2,
CPUID_7C_PKU = 1u << 3,
CPUID_7C_OSPKE = 1u << 4,
CPUID_7C_WAITPKG = 1u << 5,
CPUID_7C_AVX512VBMI2 = 1u << 6,
CPUID_7C_SHSTK = 1u << 7,
CPUID_7C_GFNI = 1u << 8,
CPUID_7C_VAES = 1u << 9,
CPUID_7C_VPCLMULQDQ = 1u << 10,
CPUID_7C_AVX512VNNI = 1u << 11,
CPUID_7C_AVX512BITALG = 1u << 12,
CPUID_7C_TME_EN = 1u << 13,
CPUID_7C_AVX512VPOPCNTDQ = 1u << 14,
CPUID_7C_RDPID = 1u << 22,
CPUID_7C_KL = 1u << 23,
CPUID_7C_CLDEMOTE = 1u << 25,
CPUID_7C_MOVDIRI = 1u << 27,
CPUID_7C_MOVDIR64B = 1u << 28,
CPUID_7C_ENQCMD = 1u << 29,
};
#define RFLAGS_CF (1u << 0)
#define RFLAGS_BRKI (1u << 1)
#define RFLAGS_PF (1u << 2)
#define RFLAGS_AF (1u << 4)
#define RFLAGS_ZF (1u << 6)
#define RFLAGS_SF (1u << 7)
#define RFLAGS_TF (1u << 8)
#define RFLAGS_IF (1u << 9)
#define RFLAGS_DF (1u << 10)
#define RFLAGS_OF (1u << 11)
#define RFLAGS_IOPL (3u << 12)
#define RFLAGS_NT (1u << 14)
#define RFLAGS_RF (1u << 16)
#define RFLAGS_VM (1u << 17)
#define RFLAGS_AC (1u << 18)
#define RFLAGS_VIF (1u << 19)
#define RFLAGS_VIP (1u << 20)
#define RFLAGS_ID (1u << 21)
enum : uint32_t {
CPUID_7D_UINTR = 1u << 5,
CPUID_7D_AVX512VP2INTERSECT = 1u << 8,
CPUID_7D_SERIALIZE = 1u << 14,
CPUID_7D_TSXLDTRK = 1u << 16,
CPUID_7D_PCONFIG = 1u << 18,
CPUID_7D_IBT = 1u << 20,
CPUID_7D_AMX_BF16 = 1u << 22,
CPUID_7D_AVX512FP16 = 1u << 23,
CPUID_7D_AMX_TILE = 1u << 24,
CPUID_7D_AMX_INT8 = 1u << 25,
};
#define XCR0_X87 (1 << 0)
#define XCR0_SSE (1 << 1)
#define XCR0_AVX (1 << 2)
#define XCR0_AXV512_OPMASK (1 << 5)
#define XCR0_AVX512_ZMM_HI256 (1 << 6)
#define XCR0_AVX512_HI16_ZMM (1 << 7)
enum : uint64_t {
RFLAGS_CF = 1ull << 0,
RFLAGS_BRKI = 1ull << 1,
RFLAGS_PF = 1ull << 2,
RFLAGS_AF = 1ull << 4,
RFLAGS_ZF = 1ull << 6,
RFLAGS_SF = 1ull << 7,
RFLAGS_TF = 1ull << 8,
RFLAGS_IF = 1ull << 9,
RFLAGS_DF = 1ull << 10,
RFLAGS_OF = 1ull << 11,
RFLAGS_IOPL = 3ull << 12,
RFLAGS_NT = 1ull << 14,
RFLAGS_RF = 1ull << 16,
RFLAGS_VM = 1ull << 17,
RFLAGS_AC = 1ull << 18,
RFLAGS_VIF = 1ull << 19,
RFLAGS_VIP = 1ull << 20,
RFLAGS_ID = 1ull << 21,
};
#define CR0_PE (1 << 0)
#define CR0_MP (1 << 1)
#define CR0_EM (1 << 2)
#define CR0_TS (1 << 3)
#define CR0_ET (1 << 4)
#define CR0_NE (1 << 5)
#define CR0_WP (1 << 16)
#define CR0_AM (1 << 18)
#define CR0_NW (1 << 29)
#define CR0_CD (1 << 30)
#define CR0_PG (1 << 31)
enum : uint64_t {
XCR0_X87 = 1ull << 0,
XCR0_SSE = 1ull << 1,
XCR0_AVX = 1ull << 2,
XCR0_AXV512_OPMASK = 1ull << 5,
XCR0_AVX512_ZMM_HI256 = 1ull << 6,
XCR0_AVX512_HI16_ZMM = 1ull << 7,
};
#define CR4_VME (1 << 0)
#define CR4_PVI (1 << 1)
#define CR4_TSD (1 << 2)
#define CR4_DE (1 << 3)
#define CR4_PSE (1 << 4)
#define CR4_PAE (1 << 5)
#define CR4_MCE (1 << 6)
#define CR4_PGE (1 << 7)
#define CR4_PCE (1 << 8)
#define CR4_OSFXSR (1 << 9)
#define CR4_OSXMMEXCPT (1 << 10)
#define CR4_UMIP (1 << 11)
#define CR4_VMXE (1 << 13)
#define CR4_SMXE (1 << 14)
#define CR4_FSGSBASE (1 << 16)
#define CR4_PCIDE (1 << 17)
#define CR4_OSXSAVE (1 << 18)
#define CR4_SMEP (1 << 20)
#define CR4_SMAP (1 << 21)
#define CR4_PKE (1 << 22)
#define CR4_CET (1 << 23)
#define CR4_PKS (1 << 24)
enum : uint64_t {
CR0_PE = 1ull << 0,
CR0_MP = 1ull << 1,
CR0_EM = 1ull << 2,
CR0_TS = 1ull << 3,
CR0_ET = 1ull << 4,
CR0_NE = 1ull << 5,
CR0_WP = 1ull << 16,
CR0_AM = 1ull << 18,
CR0_NW = 1ull << 29,
CR0_CD = 1ull << 30,
CR0_PG = 1ull << 31,
};
#define MSR_EFER_SCE (1 << 0)
#define MSR_EFER_LME (1 << 8)
#define MSR_EFER_LMA (1 << 10)
#define MSR_EFER_NXE (1 << 11)
#define MSR_EFER_SVME (1 << 12)
#define MSR_EFER_LMSLE (1 << 13)
#define MSR_EFER_FFXSR (1 << 14)
#define MSR_EFER_TCE (1 << 15)
enum : uint64_t {
CR4_VME = 1ull << 0,
CR4_PVI = 1ull << 1,
CR4_TSD = 1ull << 2,
CR4_DE = 1ull << 3,
CR4_PSE = 1ull << 4,
CR4_PAE = 1ull << 5,
CR4_MCE = 1ull << 6,
CR4_PGE = 1ull << 7,
CR4_PCE = 1ull << 8,
CR4_OSFXSR = 1ull << 9,
CR4_OSXMMEXCPT = 1ull << 10,
CR4_UMIP = 1ull << 11,
CR4_VMXE = 1ull << 13,
CR4_SMXE = 1ull << 14,
CR4_FSGSBASE = 1ull << 16,
CR4_PCIDE = 1ull << 17,
CR4_OSXSAVE = 1ull << 18,
CR4_SMEP = 1ull << 20,
CR4_SMAP = 1ull << 21,
CR4_PKE = 1ull << 22,
CR4_CET = 1ull << 23,
CR4_PKS = 1ull << 24,
};
#define MSR_PAT (0x277)
#define MSR_EFER (0xC0000080)
#define MSR_STAR (0xC0000081)
#define MSR_LSTAR (0xC0000082)
#define MSR_CSTAR (0xC0000083)
#define MSR_SFMASK (0xC0000084)
#define MSR_FS_BASE (0xC0000100)
#define MSR_GS_BASE (0xC0000101)
#define MSR_KERNEL_GS_BASE (0xC0000102)
enum : uint64_t {
MSR_EFER_SCE = 1ull << 0,
MSR_EFER_LME = 1ull << 8,
MSR_EFER_LMA = 1ull << 10,
MSR_EFER_NXE = 1ull << 11,
MSR_EFER_SVME = 1ull << 12,
MSR_EFER_LMSLE = 1ull << 13,
MSR_EFER_FFXSR = 1ull << 14,
MSR_EFER_TCE = 1ull << 15,
};
#define PAT_UC (0x0)
#define PAT_WC (0x1)
#define PAT_WT (0x4)
#define PAT_WP (0x5)
#define PAT_WB (0x6)
#define PAT_UCM (0x7)
enum : uint32_t {
MSR_PAT = 0x277,
MSR_EFER = 0xC0000080,
MSR_STAR = 0xC0000081,
MSR_LSTAR = 0xC0000082,
MSR_CSTAR = 0xC0000083,
MSR_SFMASK = 0xC0000084,
MSR_FS_BASE = 0xC0000100,
MSR_GS_BASE = 0xC0000101,
MSR_KERNEL_GS_BASE = 0xC0000102,
};
#define CPL_USER (0x3)
#define CPL_KERNEL (0x0)
enum : uint8_t {
PAT_UC = 0x0,
PAT_WC = 0x1,
PAT_WT = 0x4,
PAT_WP = 0x5,
PAT_WB = 0x6,
PAT_UCM = 0x7,
};
#define IDT_DE (0x0)
#define IDT_DB (0x1)
#define IDT_BP (0x3)
#define IDT_OF (0x4)
#define IDT_BR (0x5)
#define IDT_UD (0x6)
#define IDT_NM (0x7)
#define IDT_SS (0xC)
#define IDT_GP (0xD)
#define IDT_PF (0xE)
#define IDT_MF (0x10)
#define IDT_AC (0x11)
#define IDT_XM (0x13)
#define IDT_IPI_SHOOTDOWN (0xFC)
#define IDT_TIMER (0xFD)
#define IDT_SPURIOUS (0xFE)
#define IDT_IPI_RESCHED (0xFF)
enum : uint8_t {
CPL_USER = 0x3,
CPL_KERNEL = 0x0,
};
enum : uint8_t {
IDT_DE = 0x0,
IDT_DB = 0x1,
IDT_BP = 0x3,
IDT_OF = 0x4,
IDT_BR = 0x5,
IDT_UD = 0x6,
IDT_NM = 0x7,
IDT_SS = 0xC,
IDT_GP = 0xD,
IDT_PF = 0xE,
IDT_MF = 0x10,
IDT_AC = 0x11,
IDT_XM = 0x13,
IDT_IPI_SHOOTDOWN = 0xFC,
IDT_TIMER = 0xFD,
IDT_SPURIOUS = 0xFE,
IDT_IPI_RESCHED = 0xFF,
};