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8 Commits

Author SHA1 Message Date
marv7000 09ab2f1a83 todo 2026-09-15 22:21:27 +02:00
marv7000 9e5ed517bc refactor 2026-09-14 02:50:35 +02:00
marv7000 cf3f1f9e99 fixes 2026-08-18 01:28:35 +02:00
marv7000 ac9d47fa16 spdx 2026-08-14 21:31:01 +02:00
marv7000 40cea4dedd vdso 2026-08-13 17:22:36 +02:00
marv7000 5ee30664c5 stuff3 2026-08-11 22:31:38 +02:00
marv7000 0e2d4ed8c6 stuff2 2026-08-11 17:48:20 +02:00
marv7000 cf33867e68 stuff 2026-07-15 22:09:13 +02:00
352 changed files with 7330 additions and 14503 deletions
+1 -1
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Style:
AngledHeaders: [ "zinnia/.*", "uapi/.*" ]
AngledHeaders: [ "zinnia/.*", " kernel/.*" ]
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.config*
build/
.cache/
.wraplock
*.o
*.a
*.so
__pycache__/
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mainmenu "Zinnia Kernel Configuration"
config KERNEL_FLAVOR
string "Kernel flavor name"
default "vanilla"
source "arch/$(ARCH)/Kconfig"
source "mem/Kconfig"
source "sched/Kconfig"
source "dev/Kconfig"
-1
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@@ -1 +0,0 @@
LICENSES/ISC.txt
+21
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@@ -0,0 +1,21 @@
MIT License
Copyright (c) 2026 Marvin Friedrich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
-7
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@@ -1,7 +0,0 @@
ISC License
Copyright 2026 Marvin Friedrich and contributors
Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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This is free and unencumbered software released into the public domain.
Anyone is free to copy, modify, publish, use, compile, sell, or distribute this software, either in source code form or as a compiled binary, for any purpose, commercial or non-commercial, and by any means.
In jurisdictions that recognize copyright laws, the author or authors of this software dedicate any and all copyright interest in the software to the public domain. We make this dedication for the benefit of the public at large and to the detriment of our heirs and
successors. We intend this dedication to be an overt act of relinquishment in perpetuity of all present and future rights to this software under copyright law.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
For more information, please refer to <http://unlicense.org/>
+6 -13
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@@ -1,27 +1,20 @@
<img src="logo.svg" width="10%"/>
# Zinnia
![GitHub License](https://img.shields.io/github/license/zinnia-os/zinnia?style=flat&color=green)
![GitHub top language](https://img.shields.io/github/languages/top/zinnia-os/zinnia)
![GitHub License](https://img.shields.io/github/license/zinnia-os/zinnia?style=flat&color=blue)
![GitHub Repo stars](https://img.shields.io/github/stars/zinnia-os/zinnia?style=flat)
![GitHub Actions Workflow Status](https://img.shields.io/github/actions/workflow/status/zinnia-os/zinnia/ci.yml)
![GitHub Issues or Pull Requests](https://img.shields.io/github/issues/zinnia-os/zinnia?style=flat)
![Discord](https://img.shields.io/discord/1305893510704267327?logo=discord&logoColor=white&label=discord)
Zinnia is a lightweight Unix-like monolithic kernel targeting 64-bit devices.
Zinnia is a lightweight Unix-like microkernel targeting 64-bit devices.
## Building Zinnia
To build the kernel you need:
- `meson`
- a `kconfig` frontend (like `kconfiglib` via `pip`)
- a GNU-like C compiler with support for C23 (e.g. `gcc` or `clang`)
To build the kernel and the servers you need `meson` and a C23-compatible
GNU-like compiler targeting Zinnia.
Currently supported are GCC and Clang toolchains.
To configure, run:
```sh
alldefconfig
meson setup $build_dir
meson setup -Dbuild_kernel=true -Dbuild_servers=true $build_dir
```
And to build:
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menu "x86_64 Architecture options"
config X86_64
bool
default y
select ACPI
select HAVE_MMU
select HAVE_MMU_GENERIC
select HAVE_TLB_SHOOTDOWN_IPI
help
64-bit x86 CPU support for AMD and Intel CPUs.
config TSC
bool "Invariant Timestamp Counter support"
default y
endmenu
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#include <stdckdint.h>
#include <stdint.h>
#include <uacpi/kernel_api.h>
#include <uacpi/status.h>
#include <x86_64/asm.h>
uacpi_status uacpi_kernel_io_map(uacpi_io_addr base, uacpi_size len, uacpi_handle* out_handle) {
uintptr_t end;
if (ckd_add(&end, base, len) || end > 0x10000)
return UACPI_STATUS_INVALID_ARGUMENT;
*out_handle = (uacpi_handle)(uintptr_t)base;
return UACPI_STATUS_OK;
}
void uacpi_kernel_io_unmap(uacpi_handle handle) {
// Left intentionally blank.
}
#define IO_READ(width, suffix) \
uacpi_status uacpi_kernel_io_read##width(uacpi_handle handle, uacpi_size offset, uacpi_u##width* out_value) { \
*out_value = asm_in##suffix((uintptr_t)handle + offset); \
return UACPI_STATUS_OK; \
}
#define IO_WRITE(width, suffix) \
uacpi_status uacpi_kernel_io_write##width(uacpi_handle handle, uacpi_size offset, uacpi_u##width in_value) { \
asm_out##suffix((uintptr_t)handle + offset, in_value); \
return UACPI_STATUS_OK; \
}
IO_READ(8, b)
IO_READ(16, w)
IO_READ(32, l)
IO_WRITE(8, b)
IO_WRITE(16, w)
IO_WRITE(32, l)
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#include <zinnia/alloc.h>
#include <zinnia/assert.h>
#include <zinnia/clock.h>
#include <zinnia/mmio.h>
#include <zinnia/percpu.h>
#include <zinnia/pmap.h>
#include <zinnia/utils.h>
#include <zinnia/vma.h>
#include <arch/cpu.h>
#include <arch/timer.h>
#include <stdint.h>
#include <x86_64/apic.h>
#include <x86_64/asm.h>
#include <x86_64/defs.h>
#include <x86_64/percpu.h>
static uint32_t lapic_msr(size_t offset) {
return 0x800 + (offset >> 4);
}
static uint32_t lapic_read_reg(struct local_apic* lapic, mmio_reg32 reg) {
if (lapic->xapic_regs)
return mmio_reg_read(lapic->xapic_regs, reg);
else
return asm_rdmsr(lapic_msr(reg.offset));
}
static void lapic_write_reg(struct local_apic* lapic, mmio_reg32 reg, uint32_t value) {
if (lapic->xapic_regs)
mmio_reg_write(lapic->xapic_regs, reg, value);
else
asm_wrmsr(lapic_msr(reg.offset), value);
}
static uint64_t lapic_read_icr(struct local_apic* lapic) {
if (lapic->xapic_regs) {
uint64_t lo = mmio_reg_read(lapic->xapic_regs, APIC_REG_ICR_LO);
uint64_t hi = mmio_reg_read(lapic->xapic_regs, APIC_REG_ICR_HI);
return (hi << 32) | lo;
} else {
return asm_rdmsr(lapic_msr(APIC_REG_ICR.offset));
}
}
static void lapic_write_icr(struct local_apic* lapic, uint64_t value) {
if (lapic->xapic_regs) {
mmio_reg_write(lapic->xapic_regs, APIC_REG_ICR_HI, (uint32_t)(value >> 32));
mmio_reg_write(lapic->xapic_regs, APIC_REG_ICR_LO, (uint32_t)value);
} else {
asm_wrmsr(lapic_msr(APIC_REG_ICR.offset), value);
}
}
void lapic_init(struct local_apic* lapic) {
uint64_t apic_msr = asm_rdmsr(0x1B);
apic_msr |= 1 << 11; // Enable APIC.
struct cpuid cpuid = asm_cpuid(1, 0);
if (cpuid.ecx & CPUID_1C_X2APIC)
apic_msr |= 1 << 10;
else {
uintptr_t vaddr = vm_alloc(0x1000);
pmap_map(&kernel_vma.pmap, vaddr, apic_msr & 0xFFFF'F000, PTE_READ | PTE_WRITE, CACHE_MMIO);
lapic->xapic_regs = (void*)vaddr;
assert(lapic->xapic_regs, "Failed to allocate virtual memory!");
}
asm_wrmsr(0x1B, apic_msr);
lapic->id = lapic_read_reg(lapic, APIC_REG_ID);
if (lapic->xapic_regs)
lapic->id = mmio_field_get(APIC_ID_XAPIC, lapic->id);
// Reset the TPR.
lapic_write_reg(lapic, APIC_REG_TPR, 0);
// Enable APIC bit in the SIVR.
uint32_t sivr = lapic_read_reg(lapic, APIC_REG_SIVR);
sivr |= mmio_field(APIC_SIVR_VECTOR, IDT_SPURIOUS);
sivr |= mmio_field(APIC_SIVR_ENABLE, 1);
lapic_write_reg(lapic, APIC_REG_SIVR, sivr);
if (lapic->xapic_regs) {
lapic_write_reg(lapic, APIC_REG_DFR, 0xF000'0000);
// Logical destination = LAPIC ID.
lapic_write_reg(lapic, APIC_REG_LDR, lapic_read_reg(lapic, APIC_REG_ID));
}
// TODO: Parse MADT and setup NMI sources.
// Tell the APIC timer to divide by 16.
lapic_write_reg(lapic, APIC_REG_DCR, 3);
// Set the timer to the highest value possible.
lapic_write_reg(lapic, APIC_REG_ICR_TIMER, 0xFFFF'FFFF);
// Sleep for 10 milliseconds.
clock_spin_ns(10'000'000);
lapic->ticks_per_10ms = 0xFFFF'FFFF - lapic_read_reg(lapic, APIC_REG_CCR);
lapic_write_reg(lapic, APIC_REG_LVT_TR, mmio_field(APIC_LVT_TR_VECTOR, IDT_TIMER));
lapic_write_reg(lapic, APIC_REG_ICR_TIMER, 0);
}
void arch_timer_program(uint64_t deadline_ns) {
struct local_apic* lapic = &percpu_ref(arch_data)->lapic;
const uint64_t now = clock_get_elapsed_ns();
const uint64_t delta = MIN(deadline_ns > now ? deadline_ns - now : 0, 1'000'000'000);
const uint64_t ticks = delta * lapic->ticks_per_10ms / 10'000'000;
lapic_write_reg(lapic, APIC_REG_ICR_TIMER, MIN(MAX(ticks, 1), 0xFFFF'FFFF));
}
void lapic_eoi(struct local_apic* lapic) {
lapic_write_reg(lapic, APIC_REG_EOI, 0);
}
void lapic_send_ipi(
struct local_apic* lapic,
uint32_t target,
uint8_t vector,
enum apic_delivery_mode delivery_mode,
enum apic_dest_mode dest_mode,
enum apic_level level,
enum apic_trigger_mode trigger_mode
) {
uint64_t icr = mmio_field(APIC_ICR_VECTOR, vector);
icr |= mmio_field(APIC_ICR_DELIVERY_MODE, delivery_mode);
icr |= mmio_field(APIC_ICR_DEST_MODE, dest_mode);
icr |= mmio_field(APIC_ICR_LEVEL, level);
icr |= mmio_field(APIC_ICR_TRIGGER_MODE, trigger_mode);
if (lapic->xapic_regs)
icr |= mmio_field(APIC_ICR_DEST_XAPIC, target);
else
icr |= mmio_field(APIC_ICR_DEST_X2APIC, target);
lapic_write_icr(lapic, icr);
if (lapic->xapic_regs) {
while (mmio_field_get(APIC_ICR_DELIVERY_STATUS, lapic_read_icr(lapic)) == APIC_DELIVERY_STATUS_PENDING)
arch_cpu_pause();
}
}
constexpr uint16_t PIC1_COMMAND_PORT = 0x20;
constexpr uint16_t PIC1_DATA_PORT = 0x21;
constexpr uint16_t PIC2_COMMAND_PORT = 0xA0;
constexpr uint16_t PIC2_DATA_PORT = 0xA1;
void pic_disable() {
// We initialize the PIC properly, but completely disable it and use the APIC in favor of it.
// Remap IRQs so they start at 0x20 since interrupts 0x00..0x1F are used by CPU exceptions.
asm_outb(PIC1_COMMAND_PORT, 0x11);
asm_outb(PIC1_DATA_PORT, 0x20);
asm_outb(PIC1_DATA_PORT, 0x04);
asm_outb(PIC1_DATA_PORT, 0x01);
asm_outb(PIC1_DATA_PORT, 0xFF);
// Same for the slave PIC.
asm_outb(PIC2_COMMAND_PORT, 0x11);
asm_outb(PIC2_DATA_PORT, 0x28);
asm_outb(PIC2_DATA_PORT, 0x02);
asm_outb(PIC2_DATA_PORT, 0x01);
asm_outb(PIC2_DATA_PORT, 0xFF);
}
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#include <zinnia/errno.h>
#include <zinnia/syscall.h>
#include <arch/archctl.h>
#include <arch/mem.h>
#include <uapi/archctl.h>
#include <x86_64/asm.h>
#include <x86_64/defs.h>
struct syscall_ret arch_archctl(uintptr_t op, uintptr_t arg) {
struct syscall_ret ret = {};
switch (op) {
case __ARCHCTL_SET_FSBASE:
if (!arch_mem_addr_is_user(arg)) {
ret.error = EINVAL;
return ret;
}
asm_wrmsr(MSR_FS_BASE, arg);
return ret;
case __ARCHCTL_SET_GSBASE:
if (!arch_mem_addr_is_user(arg)) {
ret.error = EINVAL;
return ret;
}
// Update the inactive GSBASE MSR, not ours.
asm_wrmsr(MSR_KERNEL_GS_BASE, arg);
return ret;
default:
ret.error = EINVAL;
return ret;
}
}
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#include <zinnia/acpi.h>
#include <zinnia/assert.h>
#include <zinnia/clock.h>
#include <zinnia/cmdline.h>
#include <zinnia/initgraph.h>
#include <zinnia/mmio.h>
#include <zinnia/percpu.h>
#include <zinnia/pmap.h>
#include <zinnia/print.h>
#include <zinnia/utils.h>
#include <zinnia/vma.h>
#include <uacpi/acpi.h>
#include <uacpi/status.h>
#include <uacpi/tables.h>
#include <uacpi/uacpi.h>
static bool use_hpet = true;
static void hpet_option(bool use) {
use_hpet = use;
}
CMDLINE_OPTION("x86_64.hpet", "Enable High Precision Event Timer clock", hpet_option);
struct hpet {
struct clock clock;
void* regs;
uint32_t period;
};
constexpr mmio_reg64 HPET_REG_CAP = {.offset = 0x0};
constexpr mmio_field64 HPET_CAP_PERIOD = {HPET_REG_CAP, 32, 32};
constexpr mmio_reg64 HPET_REG_CFG = {.offset = 0x10};
constexpr mmio_field64 HPET_CFG_ENABLE = {HPET_REG_CFG, 0, 1};
constexpr mmio_reg64 HPET_REG_COUNTER = {.offset = 0xF0};
static void hpet_reset(struct clock* c) {
struct hpet* hpet = containerof(c, struct hpet, clock);
mmio_reg_write(hpet->regs, HPET_REG_COUNTER, 0);
}
static uint64_t hpet_get_elapsed_ns(struct clock* c) {
struct hpet* hpet = containerof(c, struct hpet, clock);
uint64_t counter = mmio_reg_read(hpet->regs, HPET_REG_COUNTER);
return (uint64_t)((__uint128_t)counter * (__uint128_t)hpet->period / 1'000'000);
}
static struct hpet hpet_clock = {
.clock = {
.name = "hpet",
.priority = 128,
.reset = hpet_reset,
.get_elapsed_ns = hpet_get_elapsed_ns,
},
};
static void hpet_init(struct boot_info*) {
if (!use_hpet)
return;
uacpi_table table = {0};
if (uacpi_table_find_by_signature("HPET", &table) != UACPI_STATUS_OK) {
log("x86_64/hpet: No HPET table found\n");
return;
}
struct acpi_hpet* hpet = table.ptr;
uintptr_t vaddr = vm_alloc(0x1000);
pmap_map(&kernel_vma.pmap, vaddr, hpet->address.address, PTE_READ | PTE_WRITE, CACHE_MMIO);
hpet_clock.regs = (void*)vaddr;
uacpi_table_unref(&table);
log("x86_64/hpet: HPET registers mapped at %p\n", hpet_clock.regs);
uint64_t cfg = mmio_reg_read(hpet_clock.regs, HPET_REG_CFG);
cfg |= mmio_field(HPET_CFG_ENABLE, 1);
mmio_reg_write(hpet_clock.regs, HPET_REG_CFG, cfg);
uint64_t cap = mmio_reg_read(hpet_clock.regs, HPET_REG_CAP);
hpet_clock.period = mmio_field_get(HPET_CAP_PERIOD, cap);
assert(clock_switch(&hpet_clock.clock), "Unable to switch to HPET!");
}
INIT_TASK(hpet_stage, "arch.x86_64.hpet", hpet_init);
INIT_DEPENDS(hpet_stage, acpi_stage);
INIT_ENTAILS(hpet_stage, percpu_stage);
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// SPDX-License-Identifier: ISC
#pragma once
static inline void arch_cpu_pause() {
asm volatile("pause");
}
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// SPDX-License-Identifier: ISC
#pragma once
#include <zinnia/elf.h>
#define ELF_ARCH_CLASS ELFCLASS64
#define ELF_ARCH_DATA ELFDATA2LSB
#define ELF_ARCH_MACHINE EM_X86_64
#define ELF_R_SYM ELF64_R_SYM
#define ELF_R_TYPE ELF64_R_TYPE
#define ELF_ST_BIND ELF64_ST_BIND
#define ELF_ST_TYPE ELF64_ST_TYPE
typedef elf64_ehdr_t elf_ehdr_t;
typedef elf64_phdr_t elf_phdr_t;
typedef elf64_dyn_t elf_dyn_t;
typedef elf64_addr_t elf_addr_t;
typedef elf64_off_t elf_off_t;
typedef elf64_nhdr_t elf_nhdr_t;
typedef elf64_auxv_t elf_auxv_t;
typedef elf64_sym_t elf_sym_t;
typedef elf64_rela_t elf_rela_t;
typedef elf64_rel_t elf_rel_t;
typedef elf64_relr_t elf_relr_t;
enum {
R_NONE = 0,
R_64 = 1,
R_COPY = 5,
R_GLOB_DAT = 6,
R_JUMP_SLOT = 7,
R_RELATIVE = 8,
R_IRELATIVE = 37,
};
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// SPDX-License-Identifier: ISC
#pragma once
#include <zinnia/mmio.h>
#include <stdint.h>
struct local_apic {
uint32_t id;
uint32_t ticks_per_10ms;
void* xapic_regs;
};
enum apic_delivery_mode {
APIC_DELIVERY_FIXED = 0b000,
APIC_DELIVERY_LOWESTPRIO = 0b001,
APIC_DELIVERY_SMI = 0b010,
APIC_DELIVERY_NMI = 0b100,
APIC_DELIVERY_INIT = 0b101,
APIC_DELIVERY_STARTUP = 0b110,
};
enum apic_dest_mode {
APIC_DEST_PHYSICAL = 0,
APIC_DEST_LOGICAL = 1,
};
enum apic_delivery_status {
APIC_DELIVERY_STATUS_IDLE = 0,
APIC_DELIVERY_STATUS_PENDING = 1,
};
enum apic_level {
APIC_LEVEL_DEASSERT = 0,
APIC_LEVEL_ASSERT = 1,
};
enum apic_trigger_mode {
APIC_TRIGGER_EDGE = 0,
APIC_TRIGGER_LEVEL = 1,
};
constexpr mmio_reg32 APIC_REG_ID = {.offset = 0x20};
constexpr mmio_field32 APIC_ID_XAPIC = {APIC_REG_ID, 24, 8};
constexpr mmio_reg32 APIC_REG_TPR = {.offset = 0x80};
constexpr mmio_reg32 APIC_REG_EOI = {.offset = 0xB0};
constexpr mmio_reg32 APIC_REG_LDR = {.offset = 0xD0};
constexpr mmio_reg32 APIC_REG_DFR = {.offset = 0xE0};
constexpr mmio_reg32 APIC_REG_SIVR = {.offset = 0xF0};
constexpr mmio_field32 APIC_SIVR_VECTOR = {APIC_REG_SIVR, 0, 8};
constexpr mmio_field32 APIC_SIVR_ENABLE = {APIC_REG_SIVR, 8, 1};
constexpr mmio_reg32 APIC_REG_ESR = {.offset = 0x280};
constexpr mmio_reg64 APIC_REG_ICR = {.offset = 0x300};
constexpr mmio_field64 APIC_ICR_VECTOR = {APIC_REG_ICR, 0, 8};
constexpr mmio_field64 APIC_ICR_DELIVERY_MODE = {APIC_REG_ICR, 8, 3};
constexpr mmio_field64 APIC_ICR_DEST_MODE = {APIC_REG_ICR, 11, 1};
constexpr mmio_field64 APIC_ICR_DELIVERY_STATUS = {APIC_REG_ICR, 12, 1};
constexpr mmio_field64 APIC_ICR_LEVEL = {APIC_REG_ICR, 14, 1};
constexpr mmio_field64 APIC_ICR_TRIGGER_MODE = {APIC_REG_ICR, 15, 1};
constexpr mmio_field64 APIC_ICR_DEST_XAPIC = {APIC_REG_ICR, 56, 8};
constexpr mmio_field64 APIC_ICR_DEST_X2APIC = {APIC_REG_ICR, 32, 32};
constexpr mmio_reg32 APIC_REG_ICR_LO = {.offset = 0x300};
constexpr mmio_reg32 APIC_REG_ICR_HI = {.offset = 0x310};
constexpr mmio_reg32 APIC_REG_LVT_TR = {.offset = 0x320};
constexpr mmio_field32 APIC_LVT_TR_VECTOR = {APIC_REG_LVT_TR, 0, 8};
constexpr mmio_reg32 APIC_REG_ICR_TIMER = {.offset = 0x380};
constexpr mmio_reg32 APIC_REG_CCR = {.offset = 0x390};
constexpr mmio_reg32 APIC_REG_DCR = {.offset = 0x3E0};
void lapic_init(struct local_apic* lapic);
void lapic_eoi(struct local_apic* lapic);
void lapic_send_ipi(
struct local_apic* lapic,
uint32_t target,
uint8_t vector,
enum apic_delivery_mode delivery_mode,
enum apic_dest_mode dest_mode,
enum apic_level level,
enum apic_trigger_mode trigger_mode
);
void pic_disable();
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// SPDX-License-Identifier: ISC
#pragma once
#include <stdint.h>
enum : uint32_t {
CPUID_1C_SSE3 = 1u << 0,
CPUID_1C_PCLMUL = 1u << 1,
CPUID_1C_DTES64 = 1u << 2,
CPUID_1C_MONITOR = 1u << 3,
CPUID_1C_DS_CPL = 1u << 4,
CPUID_1C_VMX = 1u << 5,
CPUID_1C_SMX = 1u << 6,
CPUID_1C_EST = 1u << 7,
CPUID_1C_TM2 = 1u << 8,
CPUID_1C_SSSE3 = 1u << 9,
CPUID_1C_CID = 1u << 10,
CPUID_1C_SDBG = 1u << 11,
CPUID_1C_FMA = 1u << 12,
CPUID_1C_CX16 = 1u << 13,
CPUID_1C_XTPR = 1u << 14,
CPUID_1C_PDCM = 1u << 15,
CPUID_1C_PCID = 1u << 17,
CPUID_1C_DCA = 1u << 18,
CPUID_1C_SSE4_1 = 1u << 19,
CPUID_1C_SSE4_2 = 1u << 20,
CPUID_1C_X2APIC = 1u << 21,
CPUID_1C_MOVBE = 1u << 22,
CPUID_1C_POPCNT = 1u << 23,
CPUID_1C_TSC = 1u << 24,
CPUID_1C_AES = 1u << 25,
CPUID_1C_XSAVE = 1u << 26,
CPUID_1C_OSXSAVE = 1u << 27,
CPUID_1C_AVX = 1u << 28,
CPUID_1C_F16C = 1u << 29,
CPUID_1C_RDRAND = 1u << 30,
CPUID_1C_HYPERVISOR = 1u << 31,
};
enum : uint32_t {
CPUID_1D_FPU = 1u << 0,
CPUID_1D_VME = 1u << 1,
CPUID_1D_DE = 1u << 2,
CPUID_1D_PSE = 1u << 3,
CPUID_1D_TSC = 1u << 4,
CPUID_1D_MSR = 1u << 5,
CPUID_1D_PAE = 1u << 6,
CPUID_1D_MCE = 1u << 7,
CPUID_1D_CX8 = 1u << 8,
CPUID_1D_APIC = 1u << 9,
CPUID_1D_SEP = 1u << 11,
CPUID_1D_MTRR = 1u << 12,
CPUID_1D_PGE = 1u << 13,
CPUID_1D_MCA = 1u << 14,
CPUID_1D_CMOV = 1u << 15,
CPUID_1D_PAT = 1u << 16,
CPUID_1D_PSE36 = 1u << 17,
CPUID_1D_PSN = 1u << 18,
CPUID_1D_CLFLUSH = 1u << 19,
CPUID_1D_DS = 1u << 21,
CPUID_1D_ACPI = 1u << 22,
CPUID_1D_MMX = 1u << 23,
CPUID_1D_FXSR = 1u << 24,
CPUID_1D_SSE = 1u << 25,
CPUID_1D_SSE2 = 1u << 26,
CPUID_1D_SS = 1u << 27,
CPUID_1D_HTT = 1u << 28,
CPUID_1D_TM = 1u << 29,
CPUID_1D_IA64 = 1u << 30,
CPUID_1D_PBE = 1u << 31,
};
enum : uint32_t {
CPUID_7B_FSGSBASE = 1u << 0,
CPUID_7B_SGX = 1u << 2,
CPUID_7B_BMI = 1u << 3,
CPUID_7B_HLE = 1u << 4,
CPUID_7B_AVX2 = 1u << 5,
CPUID_7B_SMEP = 1u << 7,
CPUID_7B_BMI2 = 1u << 8,
CPUID_7B_RTM = 1u << 11,
CPUID_7B_AVX512F = 1u << 16,
CPUID_7B_AVX512DQ = 1u << 17,
CPUID_7B_RDSEED = 1u << 18,
CPUID_7B_ADX = 1u << 19,
CPUID_7B_SMAP = 1u << 20,
CPUID_7B_AVX512IFMA = 1u << 21,
CPUID_7B_CLFLUSHOPT = 1u << 23,
CPUID_7B_CLWB = 1u << 24,
CPUID_7B_AVX512CD = 1u << 28,
CPUID_7B_SHA = 1u << 29,
CPUID_7B_AVX512BW = 1u << 30,
CPUID_7B_AVX512VL = 1u << 31,
};
enum : uint32_t {
CPUID_7C_AVX512VBMI = 1u << 1,
CPUID_7C_UMIP = 1u << 2,
CPUID_7C_PKU = 1u << 3,
CPUID_7C_OSPKE = 1u << 4,
CPUID_7C_WAITPKG = 1u << 5,
CPUID_7C_AVX512VBMI2 = 1u << 6,
CPUID_7C_SHSTK = 1u << 7,
CPUID_7C_GFNI = 1u << 8,
CPUID_7C_VAES = 1u << 9,
CPUID_7C_VPCLMULQDQ = 1u << 10,
CPUID_7C_AVX512VNNI = 1u << 11,
CPUID_7C_AVX512BITALG = 1u << 12,
CPUID_7C_TME_EN = 1u << 13,
CPUID_7C_AVX512VPOPCNTDQ = 1u << 14,
CPUID_7C_RDPID = 1u << 22,
CPUID_7C_KL = 1u << 23,
CPUID_7C_CLDEMOTE = 1u << 25,
CPUID_7C_MOVDIRI = 1u << 27,
CPUID_7C_MOVDIR64B = 1u << 28,
CPUID_7C_ENQCMD = 1u << 29,
};
enum : uint32_t {
CPUID_7D_UINTR = 1u << 5,
CPUID_7D_AVX512VP2INTERSECT = 1u << 8,
CPUID_7D_SERIALIZE = 1u << 14,
CPUID_7D_TSXLDTRK = 1u << 16,
CPUID_7D_PCONFIG = 1u << 18,
CPUID_7D_IBT = 1u << 20,
CPUID_7D_AMX_BF16 = 1u << 22,
CPUID_7D_AVX512FP16 = 1u << 23,
CPUID_7D_AMX_TILE = 1u << 24,
CPUID_7D_AMX_INT8 = 1u << 25,
};
enum : uint64_t {
RFLAGS_CF = 1ull << 0,
RFLAGS_BRKI = 1ull << 1,
RFLAGS_PF = 1ull << 2,
RFLAGS_AF = 1ull << 4,
RFLAGS_ZF = 1ull << 6,
RFLAGS_SF = 1ull << 7,
RFLAGS_TF = 1ull << 8,
RFLAGS_IF = 1ull << 9,
RFLAGS_DF = 1ull << 10,
RFLAGS_OF = 1ull << 11,
RFLAGS_IOPL = 3ull << 12,
RFLAGS_NT = 1ull << 14,
RFLAGS_RF = 1ull << 16,
RFLAGS_VM = 1ull << 17,
RFLAGS_AC = 1ull << 18,
RFLAGS_VIF = 1ull << 19,
RFLAGS_VIP = 1ull << 20,
RFLAGS_ID = 1ull << 21,
};
enum : uint64_t {
XCR0_X87 = 1ull << 0,
XCR0_SSE = 1ull << 1,
XCR0_AVX = 1ull << 2,
XCR0_AXV512_OPMASK = 1ull << 5,
XCR0_AVX512_ZMM_HI256 = 1ull << 6,
XCR0_AVX512_HI16_ZMM = 1ull << 7,
};
enum : uint64_t {
CR0_PE = 1ull << 0,
CR0_MP = 1ull << 1,
CR0_EM = 1ull << 2,
CR0_TS = 1ull << 3,
CR0_ET = 1ull << 4,
CR0_NE = 1ull << 5,
CR0_WP = 1ull << 16,
CR0_AM = 1ull << 18,
CR0_NW = 1ull << 29,
CR0_CD = 1ull << 30,
CR0_PG = 1ull << 31,
};
enum : uint64_t {
CR4_VME = 1ull << 0,
CR4_PVI = 1ull << 1,
CR4_TSD = 1ull << 2,
CR4_DE = 1ull << 3,
CR4_PSE = 1ull << 4,
CR4_PAE = 1ull << 5,
CR4_MCE = 1ull << 6,
CR4_PGE = 1ull << 7,
CR4_PCE = 1ull << 8,
CR4_OSFXSR = 1ull << 9,
CR4_OSXMMEXCPT = 1ull << 10,
CR4_UMIP = 1ull << 11,
CR4_VMXE = 1ull << 13,
CR4_SMXE = 1ull << 14,
CR4_FSGSBASE = 1ull << 16,
CR4_PCIDE = 1ull << 17,
CR4_OSXSAVE = 1ull << 18,
CR4_SMEP = 1ull << 20,
CR4_SMAP = 1ull << 21,
CR4_PKE = 1ull << 22,
CR4_CET = 1ull << 23,
CR4_PKS = 1ull << 24,
};
enum : uint64_t {
MSR_EFER_SCE = 1ull << 0,
MSR_EFER_LME = 1ull << 8,
MSR_EFER_LMA = 1ull << 10,
MSR_EFER_NXE = 1ull << 11,
MSR_EFER_SVME = 1ull << 12,
MSR_EFER_LMSLE = 1ull << 13,
MSR_EFER_FFXSR = 1ull << 14,
MSR_EFER_TCE = 1ull << 15,
};
enum : uint32_t {
MSR_PAT = 0x277,
MSR_EFER = 0xC0000080,
MSR_STAR = 0xC0000081,
MSR_LSTAR = 0xC0000082,
MSR_CSTAR = 0xC0000083,
MSR_SFMASK = 0xC0000084,
MSR_FS_BASE = 0xC0000100,
MSR_GS_BASE = 0xC0000101,
MSR_KERNEL_GS_BASE = 0xC0000102,
};
enum : uint8_t {
PAT_UC = 0x0,
PAT_WC = 0x1,
PAT_WT = 0x4,
PAT_WP = 0x5,
PAT_WB = 0x6,
PAT_UCM = 0x7,
};
enum : uint8_t {
CPL_USER = 0x3,
CPL_KERNEL = 0x0,
};
enum : uint8_t {
IDT_DE = 0x0,
IDT_DB = 0x1,
IDT_BP = 0x3,
IDT_OF = 0x4,
IDT_BR = 0x5,
IDT_UD = 0x6,
IDT_NM = 0x7,
IDT_SS = 0xC,
IDT_GP = 0xD,
IDT_PF = 0xE,
IDT_MF = 0x10,
IDT_AC = 0x11,
IDT_XM = 0x13,
IDT_IPI_SHOOTDOWN = 0xFC,
IDT_TIMER = 0xFD,
IDT_SPURIOUS = 0xFE,
IDT_IPI_RESCHED = 0xFF,
};
-21
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@@ -1,21 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#include <zinnia/pmap.h>
enum : pte_t {
ARCH_FLAG_PRESENT = 1 << 0,
ARCH_FLAG_READ_WRITE = 1 << 1,
ARCH_FLAG_USER_MODE = 1 << 2,
ARCH_FLAG_WRITE_THROUGH = 1 << 3,
ARCH_FLAG_CACHE_DISABLE = 1 << 4,
ARCH_FLAG_ACCESSED = 1 << 5,
ARCH_FLAG_DIRTY = 1 << 6,
ARCH_FLAG_SIZE = 1 << 7,
ARCH_FLAG_GLOBAL = 1 << 8,
ARCH_FLAG_AVAILABLE = 1 << 9,
ARCH_FLAG_ATTRIBUTE_TABLE = 1 << 7,
ARCH_FLAG_EXECUTE_DISABLE = 1LU << 63,
ARCH_PTE_ADDR_MASK = 0x000F'FFFF'FFFF'F000,
};
-26
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@@ -1,26 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#include <zinnia/atomic.h>
#include <zinnia/compiler.h>
#include <zinnia/utils.h>
#include <stdint.h>
#include <x86_64/gdt.h>
struct [[__packed]] smp_info {
struct gdt gdt;
struct gdtr gdtr;
uint32_t farjmp_offset;
uint32_t farjmp_segment;
uint32_t temp_stack;
uint32_t temp_cr3;
uint64_t entry;
uint64_t hhdm_offset;
uint64_t percpu;
uint32_t lapic_id;
atomic_bool booted;
};
// Discovers all APs and starts them.
void x86_64_smp_init();
-5
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@@ -1,5 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
void tsc_init();
-93
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@@ -1,93 +0,0 @@
#include <zinnia/alloc.h>
#include <zinnia/assert.h>
#include <zinnia/percpu.h>
#include <zinnia/utils.h>
#include <arch/irq.h>
#include <stdint.h>
#include <x86_64/apic.h>
#include <x86_64/defs.h>
#include <x86_64/percpu.h>
bool arch_irq_get_state() {
uint64_t flags;
asm volatile("pushf; pop %0" : "=r"(flags)::"memory");
return flags & RFLAGS_IF;
}
bool arch_irq_set_state(bool state) {
bool old = arch_irq_get_state();
if (state)
asm volatile("sti" ::: "memory");
else
asm volatile("cli" ::: "memory");
return old;
}
void arch_irq_wait() {
asm volatile("hlt");
}
struct apic_msi_line {
struct msi_line msi;
uint8_t vector;
uint32_t lapic;
};
static phys_t apic_msi_msg_addr(struct msi_line* self) {
struct apic_msi_line* line = containerof(self, struct apic_msi_line, msi);
return 0xFEE0'0000 | ((phys_t)line->lapic << 12);
}
static uint32_t apic_msi_msg_data(struct msi_line* self) {
return containerof(self, struct apic_msi_line, msi)->vector;
}
static enum irq_mode apic_msi_set_config(
struct irq_line* self,
enum irq_trigger_mode trigger,
enum irq_polarity polarity
) {
assert(trigger == IRQ_TRIGGER_EDGE, "MSIs must be edge triggered");
return IRQ_MODE_EOI;
}
static void apic_msi_mask(struct irq_line* self) {}
static void apic_msi_unmask(struct irq_line* self) {}
static void apic_msi_eoi(struct irq_line* self) {
lapic_eoi(&percpu_ref(arch_data)->lapic);
}
errno_t arch_irq_alloc_msi(struct msi_line** out) {
struct apic_msi_line* line = mem_alloc(sizeof(*line), 0);
if (!line)
return ENOMEM;
irq_lock();
struct arch_percpu* arch_cpu = percpu_ref(arch_data);
size_t slot;
for (slot = 0; slot < ARRAY_SIZE(arch_cpu->irq_lines); slot++) {
if (!arch_cpu->irq_lines[slot])
break;
}
if (slot == ARRAY_SIZE(arch_cpu->irq_lines)) {
irq_unlock();
mem_free(line);
return ENOSPC;
}
line->msi.line.set_config = apic_msi_set_config;
line->msi.line.mask = apic_msi_mask;
line->msi.line.unmask = apic_msi_unmask;
line->msi.line.eoi = apic_msi_eoi;
line->msi.msg_addr = apic_msi_msg_addr;
line->msi.msg_data = apic_msi_msg_data;
line->vector = slot + 0x20;
line->lapic = arch_cpu->lapic.id;
arch_cpu->irq_lines[slot] = &line->msi.line;
irq_unlock();
*out = &line->msi;
return 0;
}
-50
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@@ -1,50 +0,0 @@
#include <zinnia/init.h>
#include <zinnia/pci.h>
#include <zinnia/spin.h>
#include <x86_64/asm.h>
constexpr uint16_t PCI_CONFIG_ADDRESS = 0xcf8;
constexpr uint16_t PCI_CONFIG_DATA = 0xcfc;
static struct spinlock port_lock = {};
static void port_select(const struct pci_address* addr, uint16_t offset) {
asm_outl(
PCI_CONFIG_ADDRESS,
1u << 31 | (uint32_t)addr->bus << 16 | (uint32_t)(addr->device & 0x1f) << 11 |
(uint32_t)(addr->function & 0x7) << 8 | (offset & 0xfc)
);
}
static uint32_t port_read32(struct pci_access*, const struct pci_address* addr, uint16_t offset) {
spin_lock(&port_lock);
port_select(addr, offset);
uint32_t value = asm_inl(PCI_CONFIG_DATA);
spin_unlock(&port_lock);
return value;
}
static void port_write32(struct pci_access*, const struct pci_address* addr, uint16_t offset, uint32_t value) {
spin_lock(&port_lock);
port_select(addr, offset);
asm_outl(PCI_CONFIG_DATA, value);
spin_unlock(&port_lock);
}
static struct pci_access port_access = {
.name = "port",
.domain = 0,
.start_bus = 0,
.end_bus = 255,
.priority = PCI_ACCESS_PRIO_LEGACY,
.read32 = port_read32,
.write32 = port_write32,
};
[[__init]]
static void pci_x86_stage_init(struct boot_info*) {
pci_access_register(&port_access);
}
INIT_TASK(pci_x86_stage, "arch.x86_64.pci", pci_x86_stage_init);
INIT_DEPENDS(pci_x86_stage, mem_stage);
INIT_ENTAILS(pci_x86_stage, pci_stage);
-95
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@@ -1,95 +0,0 @@
#include <zinnia/irq.h>
#include <zinnia/percpu.h>
#include <zinnia/pmap.h>
#include <zinnia/types.h>
#include <x86_64/apic.h>
#include <x86_64/defs.h>
#include <x86_64/percpu.h>
#include <x86_64/pmap.h>
void pte_clear(pte_t* pte) {
*pte = 0;
}
void pte_write(pte_t* pte, pte_t val) {
*pte = val;
}
void pte_flush(uintptr_t vaddr) {
asm volatile("invlpg [%0]" ::"r"(vaddr) : "memory");
}
void pte_flush_all() {
uint64_t cr3;
asm volatile("mov %0, cr3" : "=r"(cr3));
asm volatile("mov cr3, %0" ::"r"(cr3) : "memory");
}
void pte_shootdown_kick(struct percpu* cpu) {
irq_lock();
lapic_send_ipi(
&percpu_ref(arch_data)->lapic,
percpu_ref_on(cpu, arch_data)->lapic.id,
IDT_IPI_SHOOTDOWN,
APIC_DELIVERY_FIXED,
APIC_DEST_PHYSICAL,
APIC_LEVEL_ASSERT,
APIC_TRIGGER_EDGE
);
irq_unlock();
}
pte_t pte_build(phys_t addr, enum pte_flags flags, enum cache_mode cache) {
pte_t result = ((pte_t)addr & ARCH_PTE_ADDR_MASK) | ARCH_FLAG_PRESENT;
if (flags & PTE_USER)
result |= ARCH_FLAG_USER_MODE;
if (flags & PTE_DIR)
result |= ARCH_FLAG_READ_WRITE;
else {
if (flags & PTE_WRITE)
result |= ARCH_FLAG_READ_WRITE;
if (!(flags & PTE_EXEC))
result |= ARCH_FLAG_EXECUTE_DISABLE;
switch (cache) {
case CACHE_ANY:
case CACHE_WRITE_BACK:
break;
case CACHE_WRITE_THROUGH:
result |= ARCH_FLAG_WRITE_THROUGH;
break;
case CACHE_MMIO:
result |= ARCH_FLAG_CACHE_DISABLE | ARCH_FLAG_WRITE_THROUGH;
break;
case CACHE_WRITE_COMBINE:
result |= ARCH_FLAG_ATTRIBUTE_TABLE | ARCH_FLAG_WRITE_THROUGH;
break;
}
}
return result;
}
pte_t pte_protect(pte_t old, enum pte_flags flags) {
pte_t result = old & ~(ARCH_FLAG_READ_WRITE | ARCH_FLAG_USER_MODE | ARCH_FLAG_EXECUTE_DISABLE);
if (flags & PTE_USER)
result |= ARCH_FLAG_USER_MODE;
if (flags & PTE_WRITE)
result |= ARCH_FLAG_READ_WRITE;
if (!(flags & PTE_EXEC))
result |= ARCH_FLAG_EXECUTE_DISABLE;
return result;
}
bool pte_is_present(pte_t* pte) {
return *pte & ARCH_FLAG_PRESENT;
}
phys_t pte_address(pte_t* pte) {
return (phys_t)(*pte & ARCH_PTE_ADDR_MASK);
}
void pmap_set(struct pmap* pt) {
asm volatile("mov cr3, %0" ::"r"(pt->root) : "memory");
}
-36
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@@ -1,36 +0,0 @@
#include <zinnia/initgraph.h>
#include <zinnia/print.h>
#include <zinnia/random.h>
#include <x86_64/asm.h>
#define CPUID_1C_RDRAND (1u << 30)
#define RDRAND_RETRIES 10
static bool rdrand_get_u64(struct random_source*, uint64_t* out) {
for (int i = 0; i < RDRAND_RETRIES; i++) {
uint64_t value;
uint8_t ok;
asm volatile("rdrand %0\n setc %1" : "=r"(value), "=qm"(ok) : : "cc");
if (ok) {
*out = value;
return true;
}
}
return false;
}
static struct random_source rdrand_source = {
.name = "x86_64.rdrand",
.quality = 100,
.get_u64 = rdrand_get_u64,
};
static void rdrand_init(struct boot_info*) {
if (asm_cpuid(1, 0).ecx & CPUID_1C_RDRAND) {
random_register(&rdrand_source);
} else {
log_warn("random: This CPU doesn't support RDRAND, ignoring\n");
}
}
INIT_TASK(rdrand_stage, "arch.x86_64.rdrand", rdrand_init);
INIT_ENTAILS(rdrand_stage, random_stage);
-272
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@@ -1,272 +0,0 @@
#include <zinnia/alloc.h>
#include <zinnia/assert.h>
#include <zinnia/compiler.h>
#include <zinnia/errno.h>
#include <zinnia/irq.h>
#include <zinnia/percpu.h>
#include <zinnia/pmap.h>
#include <zinnia/sched.h>
#include <zinnia/vma.h>
#include <arch/sched.h>
#include <bits/sched.h>
#include <stddef.h>
#include <stdint.h>
#include <string.h>
#include <x86_64/apic.h>
#include <x86_64/asm.h>
#include <x86_64/defs.h>
#include <x86_64/gdt.h>
#include <x86_64/idt.h>
#include <x86_64/percpu.h>
// The task frame consists of registers that the C ABI marks as callee-saved.
// If we don't save them, these registers are lost during a context switch.
struct task_frame {
uint64_t rbx, rbp, r12, r13, r14, r15, rip;
};
[[__naked]]
static struct task* perform_switch(uint64_t* old_rsp, uint64_t new_rsp, struct task* prev) {
asm volatile(
"sub rsp, 0x30\n" // Make room for all regs (except RIP).
"mov [rsp + %c[rbx]], rbx\n"
"mov [rsp + %c[rbp]], rbp\n"
"mov [rsp + %c[r12]], r12\n"
"mov [rsp + %c[r13]], r13\n"
"mov [rsp + %c[r14]], r14\n"
"mov [rsp + %c[r15]], r15\n"
"mov [rdi], rsp\n" // rdi = old_rsp
"mov rsp, rsi\n" // rsi = new_rsp
"mov rbx, [rsp + %c[rbx]]\n"
"mov rbp, [rsp + %c[rbp]]\n"
"mov r12, [rsp + %c[r12]]\n"
"mov r13, [rsp + %c[r13]]\n"
"mov r14, [rsp + %c[r14]]\n"
"mov r15, [rsp + %c[r15]]\n"
"add rsp, 0x30\n"
"mov rax, rdx\n"
"ret" // This will conveniently move us to the RIP we put at this stack entry.
:
: [rbx] "i"(offsetof(struct task_frame, rbx)),
[rbp] "i"(offsetof(struct task_frame, rbp)),
[r12] "i"(offsetof(struct task_frame, r12)),
[r13] "i"(offsetof(struct task_frame, r13)),
[r14] "i"(offsetof(struct task_frame, r14)),
[r15] "i"(offsetof(struct task_frame, r15))
: "memory"
);
}
struct task* arch_sched_switch(struct task* from, struct task* to) {
struct arch_percpu* cpu = percpu_ref(arch_data);
struct arch_task_context* from_ctx = &from->context;
struct arch_task_context* to_ctx = &to->context;
cpu->tss.rsp0 = kernel_stack_top(&to->kernel_stack);
if (from_ctx->fpu_region != nullptr) {
cpu->fpu_save(from_ctx->fpu_region);
from_ctx->ds = asm_read_ds();
from_ctx->es = asm_read_es();
from_ctx->fs = asm_read_fs();
from_ctx->gs = asm_read_gs();
from_ctx->fs_base = asm_rdmsr(MSR_FS_BASE);
from_ctx->gs_base = asm_rdmsr(MSR_KERNEL_GS_BASE);
}
if (to_ctx->fpu_region != nullptr) {
cpu->fpu_restore(to_ctx->fpu_region);
asm_write_ds(to_ctx->ds);
asm_write_es(to_ctx->es);
asm_write_fs(to_ctx->fs);
// If we have to change the GS segment we need to reload the MSR, otherwise we lose its value.
if (to_ctx->gs != asm_read_gs()) {
uint64_t percpu = asm_rdmsr(MSR_GS_BASE);
asm_write_gs(to_ctx->gs);
asm_wrmsr(MSR_GS_BASE, percpu);
}
asm_wrmsr(MSR_FS_BASE, to_ctx->fs_base);
asm_wrmsr(MSR_KERNEL_GS_BASE, to_ctx->gs_base);
}
return perform_switch(&from_ctx->rsp, to_ctx->rsp, from);
}
constexpr size_t FPU_FCW_OFFSET = 0;
constexpr size_t FPU_MXCSR_OFFSET = 24;
constexpr uint16_t FPU_DEFAULT_FCW = 0x37F;
constexpr uint32_t FPU_DEFAULT_MXCSR = 0x1F80;
// Calls task_entry with the correct parameters.
[[__naked]]
void task_entry_thunk() {
asm volatile(
"mov rdi, rbx\n"
"mov rsi, r12\n"
"mov rdx, rax\n"
"jmp task_entry"
:
:
: "memory", "rdi", "rsi", "rdx"
);
}
errno_t arch_task_init(
struct arch_task_context* context,
void* entry,
uintptr_t arg0,
uintptr_t stack_start,
bool is_user
) {
struct arch_percpu* cpu = percpu_ref(arch_data);
assert((stack_start & 0xF) == 0, "Task stack is not 16-byte aligned!");
// Prepare a dummy stack with an entry point function to return to.
struct task_frame* frame = (struct task_frame*)(stack_start - sizeof(uint64_t)) - 1;
frame->rbx = (uint64_t)entry;
frame->r12 = arg0;
frame->rip = (uint64_t)task_entry_thunk;
context->rsp = (uint64_t)frame;
if (is_user) {
// Allocate FPU space.
const size_t fpu_size = cpu->fpu_size;
uintptr_t fpu_base = vm_alloc(fpu_size);
if (!fpu_base)
return ENOMEM;
phys_t pages;
errno_t s = mem_phys_alloc(ALIGN_UP(fpu_size, arch_mem_page_size()) / arch_mem_page_size(), 0, &pages);
if (s) {
vm_free(fpu_base, fpu_size);
return s;
}
for (size_t i = 0; i < fpu_size; i += arch_mem_page_size())
pmap_map(&kernel_vma.pmap, fpu_base + i, pages + i, PTE_WRITE | PTE_READ, CACHE_WRITE_BACK);
context->fpu_region = (void*)fpu_base;
context->fpu_phys = pages;
const uint16_t fcw = FPU_DEFAULT_FCW;
const uint32_t mxcsr = FPU_DEFAULT_MXCSR;
memcpy((uint8_t*)fpu_base + FPU_FCW_OFFSET, &fcw, sizeof(fcw));
memcpy((uint8_t*)fpu_base + FPU_MXCSR_OFFSET, &mxcsr, sizeof(mxcsr));
context->ds = asm_read_ds();
context->es = asm_read_es();
context->fs = asm_read_fs();
context->gs = asm_read_gs();
context->fs_base = asm_rdmsr(MSR_FS_BASE);
context->gs_base = asm_rdmsr(MSR_KERNEL_GS_BASE);
}
return 0;
}
void arch_task_fini(struct arch_task_context* context) {
if (context->fpu_region == nullptr)
return;
const size_t page_size = arch_mem_page_size();
const size_t fpu_size = percpu_ref(arch_data)->fpu_size;
const uintptr_t fpu_base = (uintptr_t)context->fpu_region;
for (size_t i = 0; i < fpu_size; i += page_size)
pmap_unmap(&kernel_vma.pmap, fpu_base + i);
pmap_shootdown(&kernel_vma.pmap);
mem_phys_free(context->fpu_phys, ALIGN_UP(fpu_size, page_size) / page_size);
vm_free(fpu_base, fpu_size);
context->fpu_region = nullptr;
}
void arch_task_fork(struct arch_task_context* dst) {
if (dst->fpu_region)
percpu_ref(arch_data)->fpu_save(dst->fpu_region);
}
void arch_context_init_user(struct arch_context* ctx, uintptr_t ip, uintptr_t sp) {
*ctx = (struct arch_context){
.rip = ip,
.rsp = sp,
.rflags = 0x202,
.cs = offsetof(struct gdt, user_code64) | CPL_USER,
.ss = offsetof(struct gdt, user_data) | CPL_USER,
};
}
[[__naked]]
void arch_sched_preempt_disable() {
asm volatile(
"inc qword ptr gs:%c0\n"
"ret"
:
: "i"(offsetof(struct percpu, sched.preempt_level))
);
}
[[__naked]]
bool arch_sched_preempt_enable() {
asm volatile(
"dec qword ptr gs:%c0\n"
"setz al\n"
"movzx eax, al\n"
"ret\n"
:
: "i"(offsetof(struct percpu, sched.preempt_level))
: "cc"
);
}
void arch_sched_kick(struct percpu* cpu) {
if (!cpu->online)
return;
// The xAPIC ICR takes two writes, which must not be interleaved with an IPI sent by an interrupt handler.
irq_lock();
lapic_send_ipi(
&percpu_ref(arch_data)->lapic,
percpu_ref_on(cpu, arch_data)->lapic.id,
IDT_IPI_RESCHED,
APIC_DELIVERY_FIXED,
APIC_DEST_PHYSICAL,
APIC_LEVEL_ASSERT,
APIC_TRIGGER_EDGE
);
irq_unlock();
}
[[__naked]]
void arch_sched_jump_to_context(struct arch_context* context) {
asm volatile(
"mov rsp, rdi\n"
"jmp %0\n" ::"r"(interrupt_return)
);
}
void arch_sched_jump_to_user(uintptr_t ip, uintptr_t sp, uintptr_t arg) {
struct arch_context context = {
.rip = ip,
.rsp = sp,
.rdi = arg,
.rflags = 0x202,
.cs = offsetof(struct gdt, user_code64) | CPL_USER,
.ss = offsetof(struct gdt, user_data) | CPL_USER,
};
uintptr_t percpu = asm_rdmsr(MSR_GS_BASE);
asm volatile(
"mov ds, %0\n"
"mov es, %0\n"
"mov fs, %0\n"
"mov gs, %0\n"
:
: "a"(0)
: "memory"
);
asm_wrmsr(MSR_FS_BASE, 0);
asm_wrmsr(MSR_GS_BASE, percpu);
asm_wrmsr(MSR_KERNEL_GS_BASE, 0);
arch_sched_jump_to_context(&context);
}
-359
View File
@@ -1,359 +0,0 @@
#define pr_fmt(fmt) "smp: " fmt
#include <zinnia/alloc.h>
#include <zinnia/assert.h>
#include <zinnia/atomic.h>
#include <zinnia/clock.h>
#include <zinnia/compiler.h>
#include <zinnia/irq.h>
#include <zinnia/percpu.h>
#include <zinnia/pmap.h>
#include <zinnia/print.h>
#include <zinnia/sched.h>
#include <zinnia/types.h>
#include <zinnia/utils.h>
#include <zinnia/vma.h>
#include <stddef.h>
#include <stdint.h>
#include <string.h>
#include <uacpi/acpi.h>
#include <uacpi/tables.h>
#include <x86_64/apic.h>
#include <x86_64/defs.h>
#include <x86_64/percpu.h>
#include <x86_64/pmap.h>
#include <x86_64/smp.h>
extern uint8_t smp_trampoline_start[];
extern uint8_t smp_trampoline_data[];
extern uint8_t smp_trampoline_end[];
[[__naked, __used]]
static void smp_trampoline() {
asm volatile(
".pushsection .rodata\n"
".code16\n"
".global smp_trampoline_start\n"
"smp_trampoline_start:\n"
" cli\n"
" cld\n"
" jmp .Lmode16\n"
".org smp_trampoline_start + %c[data_off]\n"
".global smp_trampoline_data\n"
"smp_trampoline_data:\n"
" .skip %c[info_size]\n"
".set .Ldata_offset, %c[data_off]\n"
".set .Lgdtr_offset, (.Ldata_offset + %c[gdtr])\n"
".set .Lfarjmp_offset, (.Ldata_offset + %c[farjmp])\n"
".set .Ltemp_stack_offset, (.Ldata_offset + %c[temp_stack])\n"
".set .Ltemp_cr3_offset, (.Ldata_offset + %c[temp_cr3])\n"
".set .Lentry_offset, (.Ldata_offset + %c[entry])\n"
".set .Lhhdm_offset, (.Ldata_offset + %c[hhdm])\n"
".set .Linvalid_idtr_offset, (.Linvalid_idtr - smp_trampoline_start)\n"
".set .Lmode32_offset, (.Lmode32 - smp_trampoline_start)\n"
".set .Lmode64_offset, (.Lmode64 - smp_trampoline_start)\n"
".Lmode16:\n"
" mov bx, cs\n"
" shl ebx, 4\n"
" lidtd cs:.Linvalid_idtr_offset\n"
" lgdtd cs:.Lgdtr_offset\n"
" lea eax, [ebx + .Lmode32_offset]\n"
" mov dword ptr cs:.Lfarjmp_offset, eax\n"
" mov eax, %c[cr0]\n"
" mov cr0, eax\n"
" jmp fword ptr cs:.Lfarjmp_offset\n"
".code32\n"
".Lmode32:\n"
" mov ax, %c[kernel32_ds]\n"
" mov ds, ax\n"
" mov es, ax\n"
" mov fs, ax\n"
" mov gs, ax\n"
" mov ss, ax\n"
" xor eax, eax\n"
" lldt ax\n"
" mov esp, dword ptr [ebx + .Ltemp_stack_offset]\n"
" xor eax, eax\n"
" mov cr4, eax\n"
" or eax, %c[cr4_pae]\n"
" mov cr4, eax\n"
" mov ecx, %c[msr_efer]\n"
" mov eax, %c[efer_lme]\n"
" xor edx, edx\n"
" wrmsr\n"
" mov eax, dword ptr [ebx + .Ltemp_cr3_offset]\n"
" mov cr3, eax\n"
" mov eax, cr0\n"
" or eax, %c[cr0_pg]\n"
" mov cr0, eax\n"
" lea eax, [ebx + .Lmode64_offset]\n"
" push %c[kernel64_cs]\n"
" push eax\n"
" retf\n"
".code64\n"
".Lmode64:\n"
" mov ax, %c[kernel64_ds]\n"
" mov ds, ax\n"
" mov es, ax\n"
" mov fs, ax\n"
" mov gs, ax\n"
" mov ss, ax\n"
" mov ecx, %c[msr_efer]\n"
" rdmsr\n"
" or eax, %c[efer_nxe]\n"
" wrmsr\n"
" xor ebp, ebp\n"
" lea rdi, [rbx + .Ldata_offset]\n"
" mov rax, [rbx + .Lentry_offset]\n"
" add rsp, [rbx + .Lhhdm_offset]\n"
" jmp rax\n"
".Linvalid_idtr:\n"
" .word 0\n"
" .quad 0\n"
".global smp_trampoline_end\n"
"smp_trampoline_end:\n"
".popsection\n"
" ud2\n"
:
: [data_off] "i"(8),
[info_size] "i"(sizeof(struct smp_info)),
[gdtr] "i"(offsetof(struct smp_info, gdtr)),
[farjmp] "i"(offsetof(struct smp_info, farjmp_offset)),
[temp_stack] "i"(offsetof(struct smp_info, temp_stack)),
[temp_cr3] "i"(offsetof(struct smp_info, temp_cr3)),
[entry] "i"(offsetof(struct smp_info, entry)),
[hhdm] "i"(offsetof(struct smp_info, hhdm_offset)),
[kernel32_ds] "i"(offsetof(struct gdt, kernel_data32)),
[kernel64_cs] "i"(offsetof(struct gdt, kernel_code64)),
[kernel64_ds] "i"(offsetof(struct gdt, kernel_data64)),
[cr0] "i"(CR0_PE | CR0_ET),
[cr0_pg] "i"((uint32_t)CR0_PG),
[cr4_pae] "i"(CR4_PAE),
[msr_efer] "i"(MSR_EFER),
[efer_lme] "i"(MSR_EFER_LME),
[efer_nxe] "i"(MSR_EFER_NXE)
);
}
constexpr size_t AP_BOOT_STACK_SIZE = 0x8000;
constexpr uint64_t AP_BOOT_TIMEOUT_NS = 1'000'000'000;
[[noreturn]]
static void ap_entry(phys_t info_addr) {
// We're still running on the temporary page table.
pmap_set(&kernel_vma.pmap);
struct smp_info* info = HHDM_PTR(info_addr);
struct percpu* cpu = (struct percpu*)info->percpu;
x86_64_cpu_setup(cpu);
irq_lock();
// This task keeps running on the boot stack, but is never scheduled again after the first yield.
sched_init(&cpu->sched);
// Let the BSP know that we're alive.
// `info` must not be touched after this point.
atomic_store(&info->booted, 1, ATOMIC_RELEASE);
log("CPU %zu online\n", cpu->id);
sched_yield(&cpu->sched);
unreachable();
}
static bool start_ap(phys_t trampoline, uint32_t temp_cr3, uint32_t lapic_id) {
const size_t trampoline_size = smp_trampoline_end - smp_trampoline_start;
phys_t stack;
if (mem_phys_alloc(AP_BOOT_STACK_SIZE / arch_mem_page_size(), ALLOC_MEM32 | ALLOC_NOZERO, &stack)) {
log_err("Failed to allocate a boot stack for LAPIC %u\n", lapic_id);
return false;
}
struct percpu* cpu = percpu_new();
if (!cpu) {
log_err("Failed to allocate per-CPU data for LAPIC %u\n", lapic_id);
mem_phys_free(stack, AP_BOOT_STACK_SIZE / arch_mem_page_size());
return false;
}
log("Starting CPU %zu\n", cpu->id);
memcpy(HHDM_PTR(trampoline), smp_trampoline_start, trampoline_size);
const phys_t info_addr = trampoline + (smp_trampoline_data - smp_trampoline_start);
struct smp_info* info = HHDM_PTR(info_addr);
memcpy(&info->gdt, &gdt_base, sizeof(info->gdt));
info->gdtr.limit = sizeof(struct gdt) - 1;
info->gdtr.base = (struct gdt*)(info_addr + offsetof(struct smp_info, gdt));
info->farjmp_offset = 0; // Filled in by the trampoline.
info->farjmp_segment = offsetof(struct gdt, kernel_code32);
info->temp_stack = stack + AP_BOOT_STACK_SIZE;
info->temp_cr3 = temp_cr3;
info->entry = (uint64_t)ap_entry;
info->hhdm_offset = mem_hhdm_base;
info->percpu = (uint64_t)cpu;
info->lapic_id = lapic_id;
atomic_init(&info->booted, 0);
struct local_apic* lapic = &percpu_ref(arch_data)->lapic;
lapic_send_ipi(lapic, lapic_id, 0, APIC_DELIVERY_INIT, APIC_DEST_PHYSICAL, APIC_LEVEL_ASSERT, APIC_TRIGGER_EDGE);
clock_spin_ns(10'000'000);
lapic_send_ipi(
lapic,
lapic_id,
trampoline >> 12,
APIC_DELIVERY_STARTUP,
APIC_DEST_PHYSICAL,
APIC_LEVEL_ASSERT,
APIC_TRIGGER_EDGE
);
clock_spin_ns(10'000'000);
for (uint64_t waited = 0; !atomic_load(&info->booted, ATOMIC_ACQUIRE); waited += 1'000'000) {
if (waited >= AP_BOOT_TIMEOUT_NS) {
// The per-CPU data and boot stack are leaked on purpose, in case the AP still comes up.
log_err("CPU %zu (LAPIC %u) did not respond\n", cpu->id, lapic_id);
return false;
}
clock_spin_ns(1'000'000);
}
return true;
}
static errno_t build_temp_table(phys_t* out) {
const size_t pgsz = arch_mem_page_size();
phys_t mem;
errno_t status = mem_phys_alloc(6, ALLOC_MEM32, &mem);
if (status)
return status;
uint64_t* l4 = HHDM_PTR(mem);
uint64_t* l3 = HHDM_PTR(mem + pgsz);
const phys_t l2_base = mem + 2 * pgsz;
// Use 2 MiB pages.
l4[0] = (mem + pgsz) | ARCH_FLAG_PRESENT | ARCH_FLAG_READ_WRITE;
for (size_t i = 0; i < 4; i++) {
uint64_t* l2 = HHDM_PTR(l2_base + i * pgsz);
l3[i] = (l2_base + i * pgsz) | ARCH_FLAG_PRESENT | ARCH_FLAG_READ_WRITE;
for (size_t j = 0; j < 512; j++)
l2[j] = ((i << 30) + (j << 21)) | ARCH_FLAG_PRESENT | ARCH_FLAG_READ_WRITE | ARCH_FLAG_SIZE;
}
// Copy over the higher half from the kernel page table.
const uint64_t* kernel_l4 = HHDM_PTR(kernel_vma.pmap.root);
for (size_t i = 256; i < 512; i++)
l4[i] = kernel_l4[i];
*out = mem;
return 0;
}
void x86_64_smp_init() {
const size_t trampoline_size = smp_trampoline_end - smp_trampoline_start;
assert(trampoline_size <= arch_mem_page_size(), "SMP trampoline doesn't fit in a page");
const size_t max_cpus = percpu_max_cpus();
if (max_cpus <= 1)
return;
uacpi_table table;
if (uacpi_table_find_by_signature(ACPI_MADT_SIGNATURE, &table) != UACPI_STATUS_OK) {
log_warn("No MADT found, not starting any APs\n");
return;
}
phys_t trampoline;
if (mem_phys_alloc(1, ALLOC_MEM20, &trampoline)) {
log_err("Failed to allocate 20-bit memory for the AP trampoline\n");
uacpi_table_unref(&table);
return;
}
phys_t temp_table;
if (build_temp_table(&temp_table)) {
log_err("Failed to allocate a temporary page table\n");
mem_phys_free(trampoline, 1);
uacpi_table_unref(&table);
return;
}
const uint32_t bsp_id = percpu_ref(arch_data)->lapic.id;
bool all_booted = true;
size_t num_cpus = 1;
const struct acpi_madt* madt = table.ptr;
const uint8_t* entry = (const uint8_t*)madt->entries;
const uint8_t* end = (const uint8_t*)madt + madt->hdr.length;
while (entry + sizeof(struct acpi_entry_hdr) <= end && num_cpus < max_cpus) {
const struct acpi_entry_hdr* hdr = (const struct acpi_entry_hdr*)entry;
// Don't trust malformed firmware tables.
if (hdr->length < sizeof(struct acpi_entry_hdr) || entry + hdr->length > end) {
log_warn("MADT contains a malformed entry\n");
break;
}
uint32_t lapic_id = 0;
bool enabled = false;
switch (hdr->type) {
case ACPI_MADT_ENTRY_TYPE_LAPIC:
const struct acpi_madt_lapic* lapic = (const struct acpi_madt_lapic*)hdr;
lapic_id = lapic->id;
enabled = lapic->flags & ACPI_PIC_ENABLED;
break;
case ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC:
const struct acpi_madt_x2apic* x2apic = (const struct acpi_madt_x2apic*)hdr;
lapic_id = x2apic->id;
enabled = x2apic->flags & ACPI_PIC_ENABLED;
break;
}
if (enabled && lapic_id != bsp_id) {
if (start_ap(trampoline, temp_table, lapic_id))
num_cpus++;
else
all_booted = false;
}
entry += hdr->length;
}
uacpi_table_unref(&table);
// An AP which didn't respond might still be using these.
if (all_booted) {
mem_phys_free(temp_table, 6);
mem_phys_free(trampoline, 1);
}
log("%zu CPU(s) online\n", num_cpus);
}
-19
View File
@@ -1,19 +0,0 @@
#include <zinnia/compiler.h>
#include <zinnia/errno.h>
#include <zinnia/init.h>
#include <zinnia/percpu.h>
#include <uapi/archctl.h>
#include <x86_64/apic.h>
#include <x86_64/asm.h>
#include <x86_64/defs.h>
#include <x86_64/gdt.h>
[[__init, __naked, __used]]
void _start() {
asm volatile(
"mov rsp, %0\n"
"jmp %1"
:
: "r"(__ld_stack_top), "r"(kernel_entry)
);
}
-73
View File
@@ -1,73 +0,0 @@
#include <zinnia/compiler.h>
#include <zinnia/percpu.h>
#include <zinnia/syscall.h>
#include <bits/sched.h>
#include <stddef.h>
#include <x86_64/defs.h>
#include <x86_64/gdt.h>
// TODO: Refactor to only push callee-saved registers.
[[__naked]]
void arch_syscall_stub() {
asm volatile(
" swapgs\n"
" mov gs:%c[user_stack], rsp\n"
" mov rsp, gs:%c[kernel_stack]\n"
" cld\n"
"1:\n"
" push %c[user_data]\n" // ss
" push gs:%c[user_stack]\n"
" push r11\n" // rflags
" push %c[user_code64]\n" // cs
" push rcx\n" // rip
" push 0x00\n" // arch_context::error
" push 0x00\n" // arch_context::isr
" push rax\n"
" push rbx\n"
" push rcx\n"
" push rdx\n"
" push rbp\n"
" push rdi\n"
" push rsi\n"
" push r8\n"
" push r9\n"
" push r10\n"
" push r11\n"
" push r12\n"
" push r13\n"
" push r14\n"
" push r15\n"
" xor rbp, rbp\n"
" mov rdi, rsp\n" // SysV ABI first argument.
" call syscall_dispatch\n" // Call syscall handler.
" cli\n"
" pop r15\n"
" pop r14\n"
" pop r13\n"
" pop r12\n"
" pop r11\n"
" pop r10\n"
" pop r9\n"
" pop r8\n"
" pop rsi\n"
" pop rdi\n"
" pop rbp\n"
" pop rdx\n"
" pop rcx\n"
" pop rbx\n"
" pop rax\n"
" add rsp, 0x10\n" // Skip .error and .isr fields
" pop rcx\n" // rip
" add rsp, 0x08\n" // Skip cs
" pop r11\n" // rflags
" pop rsp\n" // rsp
" swapgs\n"
" sysretq\n"
:
: [user_stack] "i"(offsetof(struct percpu, user_stack)),
[kernel_stack] "i"(offsetof(struct percpu, kernel_stack)),
[user_code64] "i"(offsetof(struct gdt, user_code64) | CPL_USER),
[user_data] "i"(offsetof(struct gdt, user_data) | CPL_USER)
);
}
-88
View File
@@ -1,88 +0,0 @@
#define pr_fmt(fmt) "x86_64/tsc: " fmt
#include <zinnia/clock.h>
#include <zinnia/cmdline.h>
#include <zinnia/print.h>
#include <zinnia/utils.h>
#include <stdint.h>
#include <x86_64/asm.h>
#include <x86_64/defs.h>
static bool use_tsc = true;
static void tsc_option(bool opt) {
use_tsc = opt;
}
CMDLINE_OPTION("x86_64.tsc", "Enable timestamp counter", tsc_option);
constexpr uint64_t nanos_per_sec = 1'000'000'000;
static uint64_t tsc_freq = 0;
static uint64_t tsc_base_cycles = 0;
static uint64_t cycles_to_ns(uint64_t cycles, uint64_t freq) {
uint64_t seconds = cycles / freq;
uint64_t remaining_cycles = cycles % freq;
uint64_t fractional_ns = (uint64_t)((__uint128_t)remaining_cycles * (__uint128_t)nanos_per_sec / (__uint128_t)freq);
uint64_t ns = seconds * nanos_per_sec + fractional_ns;
return MIN(ns, UINT64_MAX);
}
static void tsc_reset(struct clock* clock) {
tsc_base_cycles = asm_rdtsc();
}
static uint64_t tsc_get_elapsed_ns(struct clock* clock) {
uint64_t cycles = asm_rdtsc() - tsc_base_cycles;
return cycles_to_ns(cycles, tsc_freq);
}
static struct clock tsc_clock = {
.name = "tsc",
.priority = 255,
.reset = tsc_reset,
.get_elapsed_ns = tsc_get_elapsed_ns,
};
void tsc_init() {
if (!use_tsc) {
log_warn("TSC disabled on the command line");
return;
}
if (!(asm_cpuid(1, 0).edx & CPUID_1D_TSC) || !(asm_cpuid(0x8000'0007, 0).edx & (1 << 8))) {
log_warn("No invariant TSC detected!\n");
return;
}
// Check for the TSC info leaf.
bool has_tsc_leaf = false;
struct cpuid tsc_leaf = {0};
if (asm_cpuid(0, 0).eax >= 0x15) {
tsc_leaf = asm_cpuid(0x15, 0);
has_tsc_leaf = true;
}
if (clock_available()) {
// Calibrate using existing clock.
uint64_t t1 = asm_rdtsc();
clock_spin_ns(10'000'000);
uint64_t t2 = asm_rdtsc();
tsc_freq = (t2 - t1) * 100;
} else if (has_tsc_leaf) {
// If we have no timer (yet), the only way we can calibrate the TSC is if CPUID gives us the frequency.
// On a normal system, this should usually never be called and is a last resort
// since at this point we have at least the HPET timer.
if (tsc_leaf.ecx != 0 && tsc_leaf.ebx != 0 && tsc_leaf.eax != 0) {
log("Calibrating TSC using CPUID 0x15");
tsc_freq = (uint64_t)tsc_leaf.ecx * tsc_leaf.ebx / tsc_leaf.eax;
} else {
log_err("Unable to calibrate TSC using CPUID frequency information");
return;
}
} else {
log_err("Unable to calibrate the TSC without a clock or static frequency info!\n");
return;
}
log("Timer frequency is %lu MHz\n", tsc_freq / 1'000'000);
clock_switch(&tsc_clock);
}
-142
View File
@@ -1,142 +0,0 @@
#include <zinnia/compiler.h>
#include <zinnia/percpu.h>
#include <arch/usercopy.h>
#include <x86_64/percpu.h>
void arch_usercopy_allow(bool state) {
if (!percpu_ref(arch_data)->can_smap)
return;
if (state) {
asm volatile("stac" ::: "memory");
} else {
asm volatile("clac" ::: "memory");
}
}
extern void x86_64_read_start();
extern void x86_64_read_end();
extern void x86_64_read_fault();
static const struct usercopy_region read_region = {
.start_ip = x86_64_read_start,
.end_ip = x86_64_read_end,
.fault_ip = x86_64_read_fault,
};
[[__naked]]
bool arch_usercopy_read(void* dst, const __user void* src, size_t len, struct usercopy_region** region) {
asm volatile(
// Setup regs for `rep movsb`.
" xchg rcx, rdx\n"
" lea rax, [rip + %0]\n"
" xchg [rdx], rax\n"
".global x86_64_read_start\n"
" x86_64_read_start:\n"
" rep movsb\n"
".global x86_64_read_end\n"
"x86_64_read_end:\n"
" xor rax, rax\n"
" xchg [rdx], rax\n"
" mov rax, 1\n"
" ret\n"
".global x86_64_read_fault\n"
"x86_64_read_fault:\n"
" xor rax, rax\n"
" mov [rdx], rax\n"
" ret\n"
:
: "i"(&read_region)
: "memory"
);
}
extern void x86_64_write_start();
extern void x86_64_write_end();
extern void x86_64_write_fault();
static const struct usercopy_region write_region = {
.start_ip = x86_64_write_start,
.end_ip = x86_64_write_end,
.fault_ip = x86_64_write_fault,
};
[[__naked]]
bool arch_usercopy_write(__user void* dst, const void* src, size_t len, struct usercopy_region** region) {
asm volatile(
// Setup regs for `rep movsb`.
" xchg rcx, rdx\n"
" lea rax, [rip + %0]\n"
" mov [rdx], rax\n"
".global x86_64_write_start\n"
" x86_64_write_start:\n"
" rep movsb\n"
".global x86_64_write_end\n"
" x86_64_write_end:\n"
" xor rax, rax\n"
" xchg [rdx], rax\n"
" mov rax, 1\n"
" ret\n"
".global x86_64_write_fault\n"
"x86_64_write_fault:\n"
" xor rax, rax\n"
" mov [rdx], rax\n"
" ret\n"
:
: "i"(&write_region)
: "memory"
);
}
extern void x86_64_strlen_start();
extern void x86_64_strlen_end();
extern void x86_64_strlen_fault();
static const struct usercopy_region strlen_region = {
.start_ip = x86_64_strlen_start,
.end_ip = x86_64_strlen_end,
.fault_ip = x86_64_strlen_fault,
};
[[__naked]]
bool arch_usercopy_strlen(const __user char* str, size_t max, size_t* len, struct usercopy_region** region) {
asm volatile(
" lea rax, [rip + %0]\n"
" xchg [rcx], rax\n"
".global x86_64_strlen_start\n"
" x86_64_strlen_start:\n"
" xor r8, r8\n"
".Lloop:\n"
" cmp r8, rsi\n"
" je .Lleave\n"
" cmp byte ptr [rdi + r8], 0\n"
" je .Lleave\n"
" inc r8\n"
" jmp .Lloop\n"
".Lleave:\n"
" mov [rdx], r8\n"
".global x86_64_strlen_end\n"
"x86_64_strlen_end:\n"
" xor rax, rax\n"
" xchg [rcx], rax\n"
" mov rax, 1\n"
" ret\n"
".global x86_64_strlen_fault\n"
"x86_64_strlen_fault:\n"
" xor rax, rax\n"
" mov [rcx], rax\n"
" ret\n"
:
: "i"(&strlen_region)
: "memory"
);
}
-669
View File
@@ -1,669 +0,0 @@
/* SPDX-License-Identifier: 0BSD */
/* Copyright (C) 2022-2026 Mintsuki and contributors.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef LIMINE_H
#define LIMINE_H 1
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Misc */
#ifdef LIMINE_NO_POINTERS
# define LIMINE_PTR(TYPE) uint64_t
#else
# define LIMINE_PTR(TYPE) TYPE
#endif
#define LIMINE_REQUESTS_START_MARKER { 0xf6b8f4b39de7d1ae, 0xfab91a6940fcb9cf, \
0x785c6ed015d3e316, 0x181e920a7852b9d9 }
#define LIMINE_REQUESTS_END_MARKER { 0xadc0e0531bb10d03, 0x9572709f31764c62 }
#define LIMINE_BASE_REVISION(N) { 0xf9562b2d5c95a6c8, 0x6a7b384944536bdc, (N) }
#define LIMINE_BASE_REVISION_SUPPORTED(VAR) ((VAR)[2] == 0)
#define LIMINE_LOADED_BASE_REVISION_VALID(VAR) ((VAR)[1] != 0x6a7b384944536bdc)
#define LIMINE_LOADED_BASE_REVISION(VAR) ((VAR)[1])
#define LIMINE_COMMON_MAGIC 0xc7b1dd30df4c8b88, 0x0a82e883a194f07b
struct limine_uuid {
uint32_t a;
uint16_t b;
uint16_t c;
uint8_t d[8];
};
#define LIMINE_MEDIA_TYPE_GENERIC 0
#define LIMINE_MEDIA_TYPE_OPTICAL 1
#define LIMINE_MEDIA_TYPE_TFTP 2
struct limine_file {
uint64_t revision;
LIMINE_PTR(void *) address;
uint64_t size;
LIMINE_PTR(char *) path;
LIMINE_PTR(char *) string;
uint32_t media_type;
uint32_t unused;
uint8_t tftp_ipv4[4];
uint32_t tftp_port;
uint32_t partition_index;
uint32_t mbr_disk_id;
struct limine_uuid gpt_disk_uuid;
struct limine_uuid gpt_part_uuid;
struct limine_uuid part_uuid;
};
/* Boot info */
#define LIMINE_BOOTLOADER_INFO_REQUEST_ID { LIMINE_COMMON_MAGIC, 0xf55038d8e2a1202f, 0x279426fcf5f59740 }
struct limine_bootloader_info_response {
uint64_t revision;
LIMINE_PTR(char *) name;
LIMINE_PTR(char *) version;
};
struct limine_bootloader_info_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_bootloader_info_response *) response;
};
/* Executable command line */
#define LIMINE_EXECUTABLE_CMDLINE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x4b161536e598651e, 0xb390ad4a2f1f303a }
struct limine_executable_cmdline_response {
uint64_t revision;
LIMINE_PTR(char *) cmdline;
};
struct limine_executable_cmdline_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_executable_cmdline_response *) response;
};
/* Firmware type */
#define LIMINE_FIRMWARE_TYPE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x8c2f75d90bef28a8, 0x7045a4688eac00c3 }
#define LIMINE_FIRMWARE_TYPE_X86BIOS 0
#define LIMINE_FIRMWARE_TYPE_EFI32 1
#define LIMINE_FIRMWARE_TYPE_EFI64 2
#define LIMINE_FIRMWARE_TYPE_SBI 3
struct limine_firmware_type_response {
uint64_t revision;
uint64_t firmware_type;
};
struct limine_firmware_type_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_firmware_type_response *) response;
};
/* Stack size */
#define LIMINE_STACK_SIZE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x224ef0460a8e8926, 0xe1cb0fc25f46ea3d }
struct limine_stack_size_response {
uint64_t revision;
};
struct limine_stack_size_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_stack_size_response *) response;
uint64_t stack_size;
};
/* HHDM */
#define LIMINE_HHDM_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x48dcf1cb8ad2b852, 0x63984e959a98244b }
struct limine_hhdm_response {
uint64_t revision;
uint64_t offset;
};
struct limine_hhdm_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_hhdm_response *) response;
};
/* Framebuffer */
#define LIMINE_FRAMEBUFFER_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x9d5827dcd881dd75, 0xa3148604f6fab11b }
#define LIMINE_FRAMEBUFFER_RGB 1
struct limine_video_mode {
uint64_t pitch;
uint64_t width;
uint64_t height;
uint16_t bpp;
uint8_t memory_model;
uint8_t red_mask_size;
uint8_t red_mask_shift;
uint8_t green_mask_size;
uint8_t green_mask_shift;
uint8_t blue_mask_size;
uint8_t blue_mask_shift;
};
struct limine_framebuffer {
LIMINE_PTR(void *) address;
uint64_t width;
uint64_t height;
uint64_t pitch;
uint16_t bpp;
uint8_t memory_model;
uint8_t red_mask_size;
uint8_t red_mask_shift;
uint8_t green_mask_size;
uint8_t green_mask_shift;
uint8_t blue_mask_size;
uint8_t blue_mask_shift;
uint8_t unused[7];
uint64_t edid_size;
LIMINE_PTR(void *) edid;
/* Response revision 1 */
uint64_t mode_count;
LIMINE_PTR(struct limine_video_mode **) modes;
};
struct limine_framebuffer_response {
uint64_t revision;
uint64_t framebuffer_count;
LIMINE_PTR(struct limine_framebuffer **) framebuffers;
};
struct limine_framebuffer_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_framebuffer_response *) response;
};
/* Flanterm FB init params */
#define LIMINE_FLANTERM_FB_INIT_PARAMS_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x3259399fe7c5f126, 0xe01c1c8c5db9d1a9 }
#define LIMINE_FLANTERM_FB_ROTATE_0 0
#define LIMINE_FLANTERM_FB_ROTATE_90 1
#define LIMINE_FLANTERM_FB_ROTATE_180 2
#define LIMINE_FLANTERM_FB_ROTATE_270 3
struct limine_flanterm_fb_init_params {
LIMINE_PTR(uint32_t *) canvas;
uint64_t canvas_size;
uint32_t ansi_colours[8];
uint32_t ansi_bright_colours[8];
uint32_t default_bg;
uint32_t default_fg;
uint32_t default_bg_bright;
uint32_t default_fg_bright;
LIMINE_PTR(void *) font;
uint64_t font_width;
uint64_t font_height;
uint64_t font_spacing;
uint64_t font_scale_x;
uint64_t font_scale_y;
uint64_t margin;
uint64_t rotation;
};
struct limine_flanterm_fb_init_params_response {
uint64_t revision;
uint64_t entry_count;
LIMINE_PTR(struct limine_flanterm_fb_init_params **) entries;
};
struct limine_flanterm_fb_init_params_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_flanterm_fb_init_params_response *) response;
};
/* Paging mode */
#define LIMINE_PAGING_MODE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x95c1a0edab0944cb, 0xa4e5cb3842f7488a }
#define LIMINE_PAGING_MODE_X86_64_4LVL 0
#define LIMINE_PAGING_MODE_X86_64_5LVL 1
#define LIMINE_PAGING_MODE_X86_64_MIN LIMINE_PAGING_MODE_X86_64_4LVL
#define LIMINE_PAGING_MODE_X86_64_DEFAULT LIMINE_PAGING_MODE_X86_64_4LVL
#define LIMINE_PAGING_MODE_AARCH64_4LVL 0
#define LIMINE_PAGING_MODE_AARCH64_5LVL 1
#define LIMINE_PAGING_MODE_AARCH64_MIN LIMINE_PAGING_MODE_AARCH64_4LVL
#define LIMINE_PAGING_MODE_AARCH64_DEFAULT LIMINE_PAGING_MODE_AARCH64_4LVL
#define LIMINE_PAGING_MODE_RISCV_SV39 0
#define LIMINE_PAGING_MODE_RISCV_SV48 1
#define LIMINE_PAGING_MODE_RISCV_SV57 2
#define LIMINE_PAGING_MODE_RISCV_MIN LIMINE_PAGING_MODE_RISCV_SV39
#define LIMINE_PAGING_MODE_RISCV_DEFAULT LIMINE_PAGING_MODE_RISCV_SV48
#define LIMINE_PAGING_MODE_LOONGARCH_4LVL 0
#define LIMINE_PAGING_MODE_LOONGARCH_MIN LIMINE_PAGING_MODE_LOONGARCH_4LVL
#define LIMINE_PAGING_MODE_LOONGARCH_DEFAULT LIMINE_PAGING_MODE_LOONGARCH_4LVL
struct limine_paging_mode_response {
uint64_t revision;
uint64_t mode;
};
struct limine_paging_mode_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_paging_mode_response *) response;
uint64_t mode;
uint64_t max_mode;
uint64_t min_mode;
};
/* MP */
#define LIMINE_MP_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x95a67b819a1b857e, 0xa0b61b723b6a73e0 }
struct limine_mp_info;
typedef void (*limine_goto_address)(struct limine_mp_info *);
#if defined (__x86_64__) || defined (__i386__)
#define LIMINE_MP_RESPONSE_X86_64_X2APIC (1 << 0)
struct limine_mp_info {
uint32_t processor_id;
uint32_t lapic_id;
uint64_t reserved;
LIMINE_PTR(limine_goto_address) goto_address;
uint64_t extra_argument;
};
struct limine_mp_response {
uint64_t revision;
uint32_t flags;
uint32_t bsp_lapic_id;
uint64_t cpu_count;
LIMINE_PTR(struct limine_mp_info **) cpus;
};
#elif defined (__aarch64__)
struct limine_mp_info {
uint32_t processor_id;
uint32_t reserved1;
uint64_t mpidr;
uint64_t reserved;
LIMINE_PTR(limine_goto_address) goto_address;
uint64_t extra_argument;
};
struct limine_mp_response {
uint64_t revision;
uint64_t flags;
uint64_t bsp_mpidr;
uint64_t cpu_count;
LIMINE_PTR(struct limine_mp_info **) cpus;
};
#elif defined (__riscv) && (__riscv_xlen == 64)
struct limine_mp_info {
uint64_t processor_id;
uint64_t hartid;
uint64_t reserved;
LIMINE_PTR(limine_goto_address) goto_address;
uint64_t extra_argument;
};
struct limine_mp_response {
uint64_t revision;
uint64_t flags;
uint64_t bsp_hartid;
uint64_t cpu_count;
LIMINE_PTR(struct limine_mp_info **) cpus;
};
#elif defined (__loongarch__) && (__loongarch_grlen == 64)
struct limine_mp_info {
uint64_t processor_id;
uint64_t phys_id;
uint64_t reserved;
LIMINE_PTR(limine_goto_address) goto_address;
uint64_t extra_argument;
};
struct limine_mp_response {
uint64_t revision;
uint64_t flags;
uint64_t bsp_phys_id;
uint64_t cpu_count;
LIMINE_PTR(struct limine_mp_info **) cpus;
};
#else
#error Unknown architecture
#endif
#define LIMINE_MP_REQUEST_X86_64_X2APIC (1 << 0)
struct limine_mp_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_mp_response *) response;
uint64_t flags;
};
/* Memory map */
#define LIMINE_MEMMAP_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x67cf3d9d378a806f, 0xe304acdfc50c3c62 }
#define LIMINE_MEMMAP_USABLE 0
#define LIMINE_MEMMAP_RESERVED 1
#define LIMINE_MEMMAP_ACPI_RECLAIMABLE 2
#define LIMINE_MEMMAP_ACPI_NVS 3
#define LIMINE_MEMMAP_BAD_MEMORY 4
#define LIMINE_MEMMAP_BOOTLOADER_RECLAIMABLE 5
#define LIMINE_MEMMAP_EXECUTABLE_AND_MODULES 6
#define LIMINE_MEMMAP_FRAMEBUFFER 7
#define LIMINE_MEMMAP_RESERVED_MAPPED 8
struct limine_memmap_entry {
uint64_t base;
uint64_t length;
uint64_t type;
};
struct limine_memmap_response {
uint64_t revision;
uint64_t entry_count;
LIMINE_PTR(struct limine_memmap_entry **) entries;
};
struct limine_memmap_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_memmap_response *) response;
};
/* Entry point */
#define LIMINE_ENTRY_POINT_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x13d86c035a1cd3e1, 0x2b0caa89d8f3026a }
typedef void (*limine_entry_point)(void);
struct limine_entry_point_response {
uint64_t revision;
};
struct limine_entry_point_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_entry_point_response *) response;
LIMINE_PTR(limine_entry_point) entry;
};
/* Executable File */
#define LIMINE_EXECUTABLE_FILE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0xad97e90e83f1ed67, 0x31eb5d1c5ff23b69 }
struct limine_executable_file_response {
uint64_t revision;
LIMINE_PTR(struct limine_file *) executable_file;
};
struct limine_executable_file_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_executable_file_response *) response;
};
/* Module */
#define LIMINE_MODULE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x3e7e279702be32af, 0xca1c4f3bd1280cee }
#define LIMINE_INTERNAL_MODULE_REQUIRED (1 << 0)
#define LIMINE_INTERNAL_MODULE_COMPRESSED (1 << 1)
struct limine_internal_module {
LIMINE_PTR(const char *) path;
LIMINE_PTR(const char *) string;
uint64_t flags;
};
struct limine_module_response {
uint64_t revision;
uint64_t module_count;
LIMINE_PTR(struct limine_file **) modules;
};
struct limine_module_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_module_response *) response;
/* Request revision 1 */
uint64_t internal_module_count;
LIMINE_PTR(struct limine_internal_module **) internal_modules;
};
/* RSDP */
#define LIMINE_RSDP_REQUEST_ID { LIMINE_COMMON_MAGIC, 0xc5e77b6b397e7b43, 0x27637845accdcf3c }
struct limine_rsdp_response {
uint64_t revision;
LIMINE_PTR(void *) address;
};
struct limine_rsdp_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_rsdp_response *) response;
};
/* SMBIOS */
#define LIMINE_SMBIOS_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x9e9046f11e095391, 0xaa4a520fefbde5ee }
struct limine_smbios_response {
uint64_t revision;
LIMINE_PTR(void *) entry_32;
LIMINE_PTR(void *) entry_64;
};
struct limine_smbios_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_smbios_response *) response;
};
/* EFI system table */
#define LIMINE_EFI_SYSTEM_TABLE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x5ceba5163eaaf6d6, 0x0a6981610cf65fcc }
struct limine_efi_system_table_response {
uint64_t revision;
LIMINE_PTR(void *) address;
};
struct limine_efi_system_table_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_efi_system_table_response *) response;
};
/* TPM event log */
#define LIMINE_TPM_EVENT_LOG_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x98e094fc7e76e979, 0xee8d8775c54e1d1f }
#define LIMINE_TPM_EVENT_LOG_FORMAT_TCG_1_2 1
#define LIMINE_TPM_EVENT_LOG_FORMAT_TCG_2 2
struct limine_tpm_event_log_response {
uint64_t revision;
uint64_t format;
uint64_t size;
LIMINE_PTR(void *) address;
};
struct limine_tpm_event_log_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_tpm_event_log_response *) response;
};
/* EFI memory map */
#define LIMINE_EFI_MEMMAP_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x7df62a431d6872d5, 0xa4fcdfb3e57306c8 }
struct limine_efi_memmap_response {
uint64_t revision;
LIMINE_PTR(void *) memmap;
uint64_t memmap_size;
uint64_t desc_size;
uint64_t desc_version;
};
struct limine_efi_memmap_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_efi_memmap_response *) response;
};
/* Date at boot */
#define LIMINE_DATE_AT_BOOT_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x502746e184c088aa, 0xfbc5ec83e6327893 }
struct limine_date_at_boot_response {
uint64_t revision;
int64_t timestamp;
};
struct limine_date_at_boot_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_date_at_boot_response *) response;
};
/* Executable address */
#define LIMINE_EXECUTABLE_ADDRESS_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x71ba76863cc55f63, 0xb2644a48c516a487 }
struct limine_executable_address_response {
uint64_t revision;
uint64_t physical_base;
uint64_t virtual_base;
};
struct limine_executable_address_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_executable_address_response *) response;
};
/* Device Tree Blob */
#define LIMINE_DTB_REQUEST_ID { LIMINE_COMMON_MAGIC, 0xb40ddb48fb54bac7, 0x545081493f81ffb7 }
struct limine_dtb_response {
uint64_t revision;
LIMINE_PTR(void *) dtb_ptr;
};
struct limine_dtb_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_dtb_response *) response;
};
/* RISC-V Boot Hart ID */
#define LIMINE_RISCV_BSP_HARTID_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x1369359f025525f9, 0x2ff2a56178391bb6 }
struct limine_riscv_bsp_hartid_response {
uint64_t revision;
uint64_t bsp_hartid;
};
struct limine_riscv_bsp_hartid_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_riscv_bsp_hartid_response *) response;
};
/* Bootloader Performance */
#define LIMINE_BOOTLOADER_PERFORMANCE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x6b50ad9bf36d13ad, 0xdc4c7e88fc759e17 }
struct limine_bootloader_performance_response {
uint64_t revision;
uint64_t reset_usec;
uint64_t init_usec;
uint64_t exec_usec;
};
struct limine_bootloader_performance_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_bootloader_performance_response *) response;
};
#define LIMINE_X86_64_KEEP_IOMMU_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x8ebaabe51f490179, 0x2aa86a59ffb4ab0f }
struct limine_x86_64_keep_iommu_response {
uint64_t revision;
};
struct limine_x86_64_keep_iommu_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_x86_64_keep_iommu_response *) response;
};
/* TSC (Timestamp Counter) Frequency */
#define LIMINE_TSC_FREQUENCY_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x10f2ee1d87d195e4, 0xf747a2b78f6ddb31 }
struct limine_tsc_frequency_response {
uint64_t revision;
uint64_t frequency;
};
struct limine_tsc_frequency_request {
uint64_t id[4];
uint64_t revision;
LIMINE_PTR(struct limine_tsc_frequency_response *) response;
};
#ifdef __cplusplus
}
#endif
#endif
-96
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@@ -1,96 +0,0 @@
#include <zinnia/alloc.h>
#include <zinnia/assert.h>
#include <zinnia/clock.h>
#include <zinnia/cmdline.h>
#include <zinnia/compiler.h>
#include <zinnia/console.h>
#include <zinnia/elf.h>
#include <zinnia/init.h>
#include <zinnia/initgraph.h>
#include <zinnia/irq.h>
#include <zinnia/module.h>
#include <zinnia/percpu.h>
#include <zinnia/print.h>
#include <zinnia/sched.h>
#include <zinnia/utils.h>
#include <zinnia/vma.h>
#include <zinnia/vmo.h>
#include <config.h>
#include <stdint.h>
static const char zinnia_banner[] = "Zinnia " ZINNIA_VERSION " " CONFIG_KERNEL_FLAVOR " (" ZINNIA_ARCH
", " ZINNIA_COMPILER_ID ", " ZINNIA_LINKER_ID ")";
static void kernel_main_task(uintptr_t arg0) {
errno_t status = 0;
struct boot_info* info = (struct boot_info*)arg0;
log("main: Hello from main task!\n");
// Finish the initgraph.
initgraph_run(nullptr, info);
module_init();
// TODO: Try to run init.
assert(info->num_files >= 1, "No init executable provided");
struct vma* init_space;
assert(vma_new(&init_space) == 0, "");
struct boot_file* file_data = &info->files[0];
struct task* init_task = nullptr;
struct paged_vmo* init_file;
status = vmo_new_phys(&init_file);
assert(status == 0, "Failed to allocate a memory object");
vmo_write(&init_file->object, 0, HHDM_PTR(file_data->data), file_data->length, nullptr);
// Load init.
const char* init_argv[] = {"init", nullptr};
const char* init_envp[] = {nullptr};
struct exec_info exec = {
.space = init_space,
.file_obj = &init_file->object,
.argv = init_argv,
.envp = init_envp,
};
vmo_unref(&init_file->object);
assert(status == 0, "Failed to load init process (%i)", status);
sched_add_task(&percpu_get()->sched, init_task);
while (true) {
irq_wait();
}
}
[[__init]]
void kernel_early_init() {
percpu_bsp_init();
percpu_get()->online = true;
irq_lock();
}
[[noreturn]]
void kernel_main(struct boot_info* info) {
cmdline_parse(info->cmdline);
log("%s\n", zinnia_banner); // Say hello!
log("Command line: %s\n", info->cmdline);
initgraph_run(sched_stage, info);
struct task* main_task;
task_create("main", &kernel_vma, kernel_main_task, (uintptr_t)info, &main_task);
sched_add_task(&percpu_get()->sched, main_task);
irq_unlock();
sched_yield(&percpu_get()->sched);
unreachable();
}
-19
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@@ -1,19 +0,0 @@
menu "Device Drivers"
config OF
bool "Support for OpenFirmware"
default y
help
Adds support for flattened device trees and OF platform drivers.
config ACPI
bool "Support for ACPI firmware"
default y
help
Adds support for ACPI firmware, tables and devices.
source "dev/block/Kconfig"
source "dev/pci/Kconfig"
source "dev/video/Kconfig"
endmenu
-19
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@@ -1,19 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#include <zinnia/init.h>
#include <zinnia/initgraph.h>
#include <zinnia/types.h>
#include <stdint.h>
INIT_EXTERN(acpi_stage);
extern phys_t acpi_rsdp_addr;
struct acpi_match {
const char* hid;
uintptr_t data;
};
#define ACPI_MATCH_HID(id) .hid = (id)
-45
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@@ -1,45 +0,0 @@
#define pr_fmt(fmt) "acpi: " fmt
#include <zinnia/acpi.h>
#include <zinnia/alloc.h>
#include <zinnia/cmdline.h>
#include <zinnia/percpu.h>
#include <zinnia/print.h>
#include <zinnia/types.h>
#include <uacpi/status.h>
#include <uacpi/tables.h>
#include <uacpi/uacpi.h>
phys_t acpi_rsdp_addr = 0;
static char table_buf[0x1000];
static bool use_acpi = true;
void use_acpi_option(bool use) {
use_acpi = use;
}
CMDLINE_OPTION("acpi", "Enable ACPI firmware subsystem", use_acpi_option);
[[__init]]
static bool acpi_stage_init(struct boot_info* info) {
if (!use_acpi) {
log_warn("ACPI disabled on the command line!\n");
return false;
}
if (!info->rsdp) {
log_warn("No RSDP was passed, unable to start ACPI subsystem!\n");
return false;
}
acpi_rsdp_addr = info->rsdp;
if (uacpi_setup_early_table_access(table_buf, sizeof(table_buf)) != UACPI_STATUS_OK) {
log_err("Failed to set up early table access!\n");
return false;
}
return true;
}
INIT_TASK(acpi_stage, "dev.acpi", acpi_stage_init);
INIT_DEPENDS(acpi_stage, mem_stage);
INIT_ENTAILS(acpi_stage, percpu_stage);
-32
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@@ -1,32 +0,0 @@
#define pr_fmt(fmt) "acpi: " fmt
#include <zinnia/acpi.h>
#include <zinnia/pci.h>
#include <zinnia/print.h>
#include <uacpi/acpi.h>
#include <uacpi/status.h>
#include <uacpi/tables.h>
[[__init]]
static void acpi_mcfg_stage_init(struct boot_info*) {
uacpi_table table = {};
if (uacpi_table_find_by_signature(ACPI_MCFG_SIGNATURE, &table) != UACPI_STATUS_OK)
return;
struct acpi_mcfg* mcfg = table.ptr;
size_t count = 0;
if (mcfg->hdr.length > sizeof(*mcfg))
count = (mcfg->hdr.length - sizeof(*mcfg)) / sizeof(struct acpi_mcfg_allocation);
for (size_t i = 0; i < count; i++) {
struct acpi_mcfg_allocation* entry = &mcfg->entries[i];
errno_t status = pci_ecam_register(entry->address, entry->segment, entry->start_bus, entry->end_bus);
if (status != 0)
log_warn("Failed to register ECAM for segment %hu: %i\n", entry->segment, status);
}
uacpi_table_unref(&table);
}
INIT_TASK(acpi_mcfg_stage, "dev.acpi.mcfg", acpi_mcfg_stage_init);
INIT_DEPENDS(acpi_mcfg_stage, acpi_stage);
INIT_ENTAILS(acpi_mcfg_stage, pci_stage);
-20
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@@ -1,20 +0,0 @@
uacpi = subproject('uacpi')
kernel_sources += uacpi.get_variable('sources')
kernel_sources += files(
'init.c',
'uacpi_glue.c',
)
if kconfig.get('CONFIG_PCI', 'n') == 'y'
kernel_sources += files('mcfg.c')
endif
kernel_includes += uacpi.get_variable('includes')
kernel_includes += include_directories('include')
kernel_c_args += [
'-DUACPI_FORMATTED_LOGGING',
'-DUACPI_BAREBONES_MODE', # TODO: Remove
'-DUACPI_OVERRIDE_TYPES',
]
-73
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@@ -1,73 +0,0 @@
#include <zinnia/acpi.h>
#include <zinnia/alloc.h>
#include <zinnia/console.h>
#include <zinnia/init.h>
#include <zinnia/mmio.h>
#include <zinnia/pmap.h>
#include <zinnia/print.h>
#include <zinnia/utils.h>
#include <zinnia/virt.h>
#include <zinnia/vma.h>
#include <arch/mem.h>
#include <stdarg.h>
#include <uacpi/kernel_api.h>
#include <uacpi/status.h>
#include <uacpi/types.h>
uacpi_status uacpi_kernel_get_rsdp(uacpi_phys_addr* out_rsdp_address) {
*out_rsdp_address = (uacpi_phys_addr)acpi_rsdp_addr;
return UACPI_STATUS_OK;
}
void* uacpi_kernel_map(uacpi_phys_addr addr, uacpi_size len) {
uintptr_t aligned_addr = ALIGN_DOWN(addr, arch_mem_page_size());
uintptr_t difference = addr - aligned_addr;
size_t aligned_len = ALIGN_UP(len + difference, arch_mem_page_size());
uintptr_t vaddr = vm_alloc(aligned_len);
if (!vaddr)
return nullptr;
for (size_t i = 0; i < aligned_len; i += arch_mem_page_size()) {
pmap_map(&kernel_vma.pmap, vaddr + i, aligned_addr + i, PTE_READ | PTE_WRITE, CACHE_ANY);
}
return (void*)(vaddr + difference);
}
void uacpi_kernel_unmap(void* addr, uacpi_size len) {
uintptr_t aligned_addr = ALIGN_DOWN((uintptr_t)addr, arch_mem_page_size());
uintptr_t difference = (uintptr_t)addr - aligned_addr;
size_t aligned_len = ALIGN_UP(len + difference, arch_mem_page_size());
for (size_t i = 0; i < aligned_len; i += arch_mem_page_size())
pmap_unmap(&kernel_vma.pmap, aligned_addr + i);
vm_free(aligned_addr, aligned_len);
}
static enum log_level acpi_log_level(uacpi_log_level lvl) {
switch (lvl) {
case UACPI_LOG_ERROR:
return LOG_ERR;
case UACPI_LOG_WARN:
return LOG_WARN;
case UACPI_LOG_INFO:
return LOG_INFO;
default:
return LOG_DEBUG;
}
}
void uacpi_kernel_log(uacpi_log_level lvl, const uacpi_char* msg, ...) {
va_list args;
va_start(args, msg);
log_vwrite_prefixed(acpi_log_level(lvl), "acpi: ", msg, args);
va_end(args);
}
void uacpi_kernel_vlog(uacpi_log_level lvl, const uacpi_char* msg, uacpi_va_list args) {
log_vwrite_prefixed(acpi_log_level(lvl), "acpi: ", msg, args);
}
-5
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@@ -1,5 +0,0 @@
menu "Block device drivers"
source "dev/block/nvme/Kconfig"
endmenu
-3
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@@ -1,3 +0,0 @@
if kconfig.get('CONFIG_NVME_CORE', 'n') != 'n'
subdir('nvme')
endif
-13
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@@ -1,13 +0,0 @@
menu "NVMe Support"
config NVME_CORE
bool
default y
config NVME_PCI
bool "NVMe via PCI transport"
default y
depends on PCI
depends on NVME_CORE
endmenu
-41
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@@ -1,41 +0,0 @@
#define pr_fmt(fmt) "nvme: " fmt
#include <zinnia/fdt.h>
#include <zinnia/module.h>
#include <zinnia/pci.h>
#include <zinnia/print.h>
#include <zinnia/utils.h>
#include <config.h>
#if CONFIG_NVME_PCI
#include "nvme_pci.h"
#endif
struct nvme_dev {
#if CONFIG_NVME_PCI
struct pci_device pci_dev;
#endif
};
errno_t nvme_init(struct module* mod) {
errno_t status = 0;
#if CONFIG_NVME_PCI
status = pci_driver_register(&nvme_driver);
#endif
return status;
}
errno_t nvme_exit(struct module* mod) {
// TODO: Unregister
return 0;
}
MODULE_ENTRY(nvme_init);
MODULE_EXIT(nvme_exit);
MODULE_DESC("NVMe Block Devices");
MODULE_AUTHOR("Marvin Friedrich");
MODULE_LICENSE("ISC");
MODULE_VERSION("1.0");
-12
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@@ -1,12 +0,0 @@
nvme_sources = files('core.c')
if kconfig.get('CONFIG_NVME_PCI', 'n') == 'y'
nvme_sources += files('pci.c')
endif
modules += {
'nvme': {
'modular': kconfig.get('CONFIG_NVME_CORE') == 'm',
'sources': nvme_sources,
},
}
-5
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@@ -1,5 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
extern struct pci_driver nvme_driver;
-23
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@@ -1,23 +0,0 @@
#include <zinnia/errno.h>
#include <zinnia/module.h>
#include <zinnia/pci.h>
static errno_t nvme_pci_probe(struct pci_device* dev, const struct pci_match* match) {
pci_log(dev, "Detected controller \n");
return 0;
}
static const struct pci_match nvme_match[] = {
// Generic NVMe device. Assume no quirks or any funny business.
{PCI_MATCH_CLASS(1, 8, 2), .data = 0},
};
MATCH_TABLE("pci", nvme_match);
struct pci_driver nvme_driver = {
.name = "nvme_pci",
.match = nvme_match,
.num_matches = ARRAY_SIZE(nvme_match),
.probe = nvme_pci_probe,
};
-3
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@@ -1,3 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
-1
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@@ -1 +0,0 @@
-3
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@@ -1,3 +0,0 @@
kernel_sources += files(
'memfiles.c',
)
-96
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@@ -1,96 +0,0 @@
#define pr_fmt(fmt) "fdt: " fmt
#include <zinnia/alloc.h>
#include <zinnia/fdt.h>
#include <zinnia/init.h>
#include <zinnia/print.h>
#include <zinnia/spin.h>
#include <zinnia/vec.h>
#include <string.h>
static struct fdt tree;
static bool tree_valid = false;
static struct spinlock driver_lock = {};
static vec(struct fdt_driver*) drivers = {};
struct fdt* fdt_get() {
return tree_valid ? &tree : nullptr;
}
static const struct fdt_match* fdt_match_table(
const struct fdt_match* table,
size_t num_matches,
struct fdt_node node
) {
for (size_t i = 0; i < num_matches; i++) {
if (fdt_node_is_compatible(node, table[i].compatible))
return &table[i];
}
return nullptr;
}
errno_t fdt_driver_register(struct fdt_driver* driver) {
if (driver->match == nullptr || driver->num_matches == 0) {
log_warn("Driver \"%s\" does not define any matches, ignoring\n", driver->name);
return 0;
}
if (!tree_valid)
return ENODEV;
spin_lock(&driver_lock);
vec_foreach(&drivers, i) {
if (strcmp(vec_elem_get(&drivers, i)->name, driver->name) == 0) {
spin_unlock(&driver_lock);
log_warn("Driver \"%s\" is already registered\n", driver->name);
return EEXIST;
}
}
errno_t status = vec_push(&drivers, driver);
spin_unlock(&driver_lock);
if (status != 0)
return status;
log("Registered platform driver \"%s\" with %zu match%s\n",
driver->name,
driver->num_matches,
driver->num_matches == 1 ? "" : "es");
for (size_t i = 0; i < driver->num_matches; i++)
log(" [%zu] = \"%s\"\n", i, driver->match[i].compatible);
for (struct fdt_node node = fdt_root(&tree); node.tree; node = fdt_next_node(node)) {
const struct fdt_match* match = fdt_match_table(driver->match, driver->num_matches, node);
if (match == nullptr)
continue;
log("Matched driver \"%s\" on rule [%zu]\n", driver->name, (size_t)(match - driver->match));
status = driver->probe(node, match);
if (status != 0)
log_warn("%s failed to probe: %i\n", driver->name, status);
}
return 0;
}
[[__init]]
static bool fdt_stage_init(struct boot_info* info) {
if (!info->dtb)
return false;
const void* blob = HHDM_PTR(info->dtb);
if (!fdt_init(&tree, blob, info->dtb_size)) {
log_warn("Unable to parse the device tree blob\n");
return false;
}
tree_valid = true;
struct fdt_prop model = fdt_property(fdt_root(&tree), "model");
if (model.tree && model.length)
log("Running on \"%.*s\"\n", (int)model.length, (const char*)model.data);
return true;
}
INIT_TASK(fdt_stage, "dev.dt", fdt_stage_init);
INIT_DEPENDS(fdt_stage, mem_stage);
-281
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@@ -1,281 +0,0 @@
#include <zinnia/fdt.h>
#include <string.h>
uint32_t fdt_read_u32(const void* data) {
const uint8_t* p = data;
return (uint32_t)p[0] << 24 | (uint32_t)p[1] << 16 | (uint32_t)p[2] << 8 | p[3];
}
uint64_t fdt_read_u64(const void* data) {
const uint8_t* p = data;
return (uint64_t)fdt_read_u32(p) << 32 | fdt_read_u32(p + 4);
}
static bool range_valid(size_t offset, size_t length, size_t total) {
return offset <= total && length <= total - offset;
}
struct token {
uint32_t kind;
size_t next;
const char* name;
const void* data;
size_t length;
};
static bool read_token(struct fdt* tree, size_t offset, struct token* token) {
if (!range_valid(offset, 4, tree->structs_len) || offset % 4)
return false;
*token = (struct token){.kind = fdt_read_u32(tree->structs + offset), .next = offset + 4};
if (token->kind == FDT_BEGIN_NODE) {
token->name = (const char*)tree->structs + token->next;
size_t left = tree->structs_len - token->next;
size_t length = strnlen(token->name, left);
if (length == left)
return false;
token->next += (length + 1 + 3) & ~(size_t)3;
} else if (token->kind == FDT_PROP) {
if (!range_valid(token->next, 8, tree->structs_len))
return false;
token->length = fdt_read_u32(tree->structs + token->next);
size_t name_offset = fdt_read_u32(tree->structs + token->next + 4);
token->next += 8;
if (name_offset >= tree->strings_len || !range_valid(token->next, token->length, tree->structs_len))
return false;
token->name = (const char*)tree->strings + name_offset;
size_t left = tree->strings_len - name_offset;
if (strnlen(token->name, left) == left || !*token->name)
return false;
token->data = tree->structs + token->next;
token->next += (token->length + 3) & ~(size_t)3;
} else if (token->kind != FDT_END_NODE && token->kind != FDT_NOP && token->kind != FDT_END) {
return false;
}
return token->next <= tree->structs_len;
}
bool fdt_init(struct fdt* tree, const void* data, size_t length) {
if (!tree)
return false;
*tree = (struct fdt){};
if (!data || length < sizeof(struct fdt_header))
return false;
const uint8_t* blob = data;
size_t total = fdt_read_u32(blob + 4);
size_t structs = fdt_read_u32(blob + 8);
size_t strings = fdt_read_u32(blob + 12);
size_t reserves = fdt_read_u32(blob + 16);
size_t strings_len = fdt_read_u32(blob + 32);
size_t structs_len = fdt_read_u32(blob + 36);
uint32_t version = fdt_read_u32(blob + 20);
uint32_t compat = fdt_read_u32(blob + 24);
if (fdt_read_u32(blob) != FDT_MAGIC || total > length || total < sizeof(struct fdt_header) || version < 17 ||
compat > 17 || compat > version || structs % 4 || reserves % 8 || structs < sizeof(struct fdt_header) ||
strings < sizeof(struct fdt_header) || reserves < sizeof(struct fdt_header) ||
!range_valid(structs, structs_len, total) || !range_valid(strings, strings_len, total) ||
(structs < strings + strings_len && strings < structs + structs_len))
return false;
size_t reserved_end = reserves;
for (;;) {
if (!range_valid(reserved_end, 16, total))
return false;
bool end = !fdt_read_u64(blob + reserved_end) && !fdt_read_u64(blob + reserved_end + 8);
reserved_end += 16;
if (end)
break;
}
if ((reserves < structs + structs_len && structs < reserved_end) ||
(reserves < strings + strings_len && strings < reserved_end))
return false;
struct fdt candidate = {
.blob = blob,
.total_size = total,
.version = version,
.compat_version = compat,
.boot_cpuid = fdt_read_u32(blob + 28),
.structs = blob + structs,
.structs_len = structs_len,
.strings = blob + strings,
.strings_len = strings_len,
};
size_t depth = 0;
bool started = false;
bool children[64] = {};
for (size_t offset = 0; offset < structs_len;) {
struct token token;
if (!read_token(&candidate, offset, &token))
return false;
if (token.kind == FDT_BEGIN_NODE) {
if (depth == 64 || (!depth && (started || *token.name)) || (depth && !*token.name))
return false;
if (depth)
children[depth - 1] = true;
children[depth++] = false;
started = true;
} else if (token.kind == FDT_END_NODE) {
if (!depth)
return false;
depth--;
} else if (token.kind == FDT_PROP) {
if (!depth || children[depth - 1])
return false;
} else if (token.kind == FDT_END) {
if (!started || depth || token.next != structs_len)
return false;
*tree = candidate;
return true;
}
offset = token.next;
}
return false;
}
struct fdt_node fdt_root(struct fdt* tree) {
struct token token;
size_t offset = 0;
if (tree && tree->blob) {
while (read_token(tree, offset, &token)) {
if (token.kind == FDT_BEGIN_NODE)
return (struct fdt_node){tree, offset};
if (token.kind != FDT_NOP)
break;
offset = token.next;
}
}
return (struct fdt_node){};
}
static struct fdt_node find_child(struct fdt_node node, const char* name, size_t length) {
struct token token;
if (!node.tree || !read_token(node.tree, node.offset, &token) || token.kind != FDT_BEGIN_NODE)
return (struct fdt_node){};
size_t depth = 0;
for (size_t offset = token.next; read_token(node.tree, offset, &token); offset = token.next) {
if (token.kind == FDT_BEGIN_NODE) {
if (!depth && strlen(token.name) == length && !memcmp(token.name, name, length))
return (struct fdt_node){node.tree, offset};
depth++;
} else if (token.kind == FDT_END_NODE) {
if (!depth)
break;
depth--;
}
}
return (struct fdt_node){};
}
struct fdt_node fdt_find(struct fdt* tree, const char* path) {
if (!path || *path != '/')
return (struct fdt_node){};
struct fdt_node node = fdt_root(tree);
path++;
while (*path && node.tree) {
size_t length = 0;
while (path[length] && path[length] != '/')
length++;
if (!length)
return (struct fdt_node){};
node = find_child(node, path, length);
path += length;
if (*path == '/')
path++;
}
return node;
}
struct fdt_prop fdt_property(struct fdt_node node, const char* name) {
struct token token;
if (!node.tree || !name || !read_token(node.tree, node.offset, &token) || token.kind != FDT_BEGIN_NODE)
return (struct fdt_prop){};
for (size_t offset = token.next; read_token(node.tree, offset, &token); offset = token.next) {
if (token.kind == FDT_PROP && !strcmp(token.name, name))
return (struct fdt_prop){node.tree, token.data, token.length};
if (token.kind == FDT_BEGIN_NODE || token.kind == FDT_END_NODE)
break;
}
return (struct fdt_prop){};
}
bool fdt_property_u32(struct fdt_node node, const char* name, uint32_t* value) {
struct fdt_prop property = fdt_property(node, name);
if (!property.tree || property.length != 4 || !value)
return false;
*value = fdt_read_u32(property.data);
return true;
}
bool fdt_property_u64(struct fdt_node node, const char* name, uint64_t* value) {
struct fdt_prop property = fdt_property(node, name);
if (!property.tree || property.length != 8 || !value)
return false;
*value = fdt_read_u64(property.data);
return true;
}
struct fdt_node fdt_next_node(struct fdt_node node) {
struct token token;
if (!node.tree || !read_token(node.tree, node.offset, &token))
return (struct fdt_node){};
for (size_t offset = token.next; read_token(node.tree, offset, &token); offset = token.next) {
if (token.kind == FDT_BEGIN_NODE)
return (struct fdt_node){node.tree, offset};
if (token.kind == FDT_END)
break;
}
return (struct fdt_node){};
}
bool fdt_node_is_compatible(struct fdt_node node, const char* compatible) {
struct fdt_prop property = fdt_property(node, "compatible");
const char* data = property.data;
for (size_t i = 0; i < property.length;) {
size_t length = strnlen(data + i, property.length - i);
if (length == property.length - i)
break;
if (!strcmp(data + i, compatible))
return true;
i += length + 1;
}
return false;
}
static uint64_t read_cells(const uint8_t* data, uint32_t cells) {
uint64_t value = 0;
for (uint32_t i = 0; i < cells; i++)
value = value << 32 | fdt_read_u32(data + i * 4);
return value;
}
bool fdt_node_reg(struct fdt_node node, size_t index, phys_t* addr, size_t* size) {
if (!node.tree)
return false;
struct fdt_node root = fdt_root(node.tree);
uint32_t addr_cells = 2;
uint32_t size_cells = 2;
fdt_property_u32(root, "#address-cells", &addr_cells);
fdt_property_u32(root, "#size-cells", &size_cells);
if (addr_cells > 2 || size_cells > 2)
return false;
struct fdt_prop reg = fdt_property(node, "reg");
const size_t stride = (addr_cells + size_cells) * 4;
if (!reg.tree || index >= reg.length / stride)
return false;
const uint8_t* entry = (const uint8_t*)reg.data + index * stride;
if (addr)
*addr = read_cells(entry, addr_cells);
if (size)
*size = read_cells(entry + addr_cells * 4, size_cells);
return true;
}
struct fdt_node fdt_find_compatible(struct fdt* tree, const char* compatible) {
if (!tree || !tree->blob || !compatible)
return (struct fdt_node){};
for (struct fdt_node node = fdt_root(tree); node.tree; node = fdt_next_node(node)) {
if (fdt_node_is_compatible(node, compatible))
return node;
}
return (struct fdt_node){};
}
-4
View File
@@ -1,4 +0,0 @@
kernel_sources += files(
'driver.c',
'fdt.c',
)
-14
View File
@@ -1,14 +0,0 @@
subdir('common')
subdir('block')
subdir('dt')
subdir('video')
if kconfig.get('CONFIG_PCI', 'n') == 'y'
subdir('pci')
endif
if kconfig.get('CONFIG_ACPI', 'n') == 'y'
subdir('acpi')
endif
module_lds = meson.current_source_dir() / 'module.ld'
-114
View File
@@ -1,114 +0,0 @@
/* Linker script for kernel modules */
ENTRY(__module_entry)
PHDRS
{
text PT_LOAD FLAGS(5);
rodata PT_LOAD FLAGS(4);
data PT_LOAD FLAGS(6);
dynamic PT_DYNAMIC FLAGS(6);
modversion 0x60000001;
modauthor 0x60000002;
moddesc 0x60000003;
modlicense 0x60000004;
modcmdline 0x60000005;
modexit 0x60000006;
modmatch 0x60000007;
}
SECTIONS
{
. = ALIGN(CONSTANT(MAXPAGESIZE));
/* Code */
.text : {
*(.init .init.*)
*(.text .text.*)
*(.fini .fini.*)
*(.plt .plt.*)
} :text
. = ALIGN(CONSTANT(MAXPAGESIZE));
/* Read-only data */
.rodata : {
*(.rodata .rodata.*)
*(.hash .hash.*)
*(.got .got.*)
*(.got.plt .got.plt.*)
} :rodata
.mod.version : {
KEEP(*(.mod.version))
} :rodata :modversion
.mod.author : {
KEEP(*(.mod.author))
} :rodata :modauthor
.mod.desc : {
KEEP(*(.mod.desc))
} :rodata :moddesc
.mod.license : {
KEEP(*(.mod.license))
} :rodata :modlicense
.cmdline : {
KEEP(*(.cmdline))
} :rodata :modcmdline
.mod.exit : {
KEEP(*(.mod.exit))
} :rodata :modexit
.mod.match : {
KEEP(*(.mod.match))
} :rodata :modmatch
. = ALIGN(CONSTANT(MAXPAGESIZE));
/* Read-Write data */
.data : {
*(.data)
*(.data.*)
} :data
/* Zero-initialized memory */
.bss : {
*(.*bss .*bss.*)
*(COMMON)
} :data
.dynsym : {
*(.dynsym .dynsym.*)
} :data
.dynstr : {
*(.dynstr .dynstr.*)
} :data
.rela.dyn : {
*(.rela.dyn .rela.dyn.*)
} :data
.relr.dyn : {
*(.relr.dyn .relr.dyn.*)
} :data
/* Dynamic tags */
.dynamic : {
*(.dynamic)
} :data :dynamic
/DISCARD/ :
{
*(.comment*)
*(.eh_frame*)
*(.rel.eh_frame*)
*(.gcc_except_table*)
*(.note*)
*(.interp)
}
}
-7
View File
@@ -1,7 +0,0 @@
menu "PCI bus drivers"
config PCI
bool "PCI core drivers"
default y
endmenu
-375
View File
@@ -1,375 +0,0 @@
#define pr_fmt(fmt) "pci: " fmt
#include <zinnia/alloc.h>
#include <zinnia/init.h>
#include <zinnia/module.h>
#include <zinnia/pci.h>
#include <zinnia/print.h>
#include <zinnia/spin.h>
#include <zinnia/vec.h>
#include <string.h>
static struct spinlock access_lock = {};
static vec(struct pci_access*) accesses = {};
static struct spinlock device_lock = {};
static vec(struct pci_device*) devices = {};
static vec(struct pci_driver*) drivers = {};
errno_t pci_access_register(struct pci_access* access) {
spin_lock(&access_lock);
errno_t status = vec_push(&accesses, access);
spin_unlock(&access_lock);
return status;
}
static bool pci_access_decodes(const struct pci_access* access, const struct pci_address* addr) {
return access->domain == addr->domain && addr->bus >= access->start_bus && addr->bus <= access->end_bus;
}
struct pci_access* pci_access_find(const struct pci_address* addr) {
struct pci_access* found = nullptr;
spin_lock(&access_lock);
vec_foreach(&accesses, i) {
struct pci_access* access = vec_elem_get(&accesses, i);
if (!pci_access_decodes(access, addr))
continue;
if (found == nullptr || access->priority > found->priority)
found = access;
}
spin_unlock(&access_lock);
return found;
}
static uint32_t cfg_read32(struct pci_access* access, const struct pci_address* addr, uint16_t offset) {
return access->read32(access, addr, offset & ~3);
}
static void cfg_write32(struct pci_access* access, const struct pci_address* addr, uint16_t offset, uint32_t value) {
access->write32(access, addr, offset & ~3, value);
}
uint32_t pci_read32(struct pci_device* dev, uint16_t offset) {
return cfg_read32(dev->access, &dev->address, offset);
}
uint16_t pci_read16(struct pci_device* dev, uint16_t offset) {
return pci_read32(dev, offset) >> ((offset & 2) * 8);
}
uint8_t pci_read8(struct pci_device* dev, uint16_t offset) {
return pci_read32(dev, offset) >> ((offset & 3) * 8);
}
void pci_write32(struct pci_device* dev, uint16_t offset, uint32_t value) {
cfg_write32(dev->access, &dev->address, offset, value);
}
void pci_write16(struct pci_device* dev, uint16_t offset, uint16_t value) {
uint32_t shift = (offset & 2) * 8;
uint32_t reg = pci_read32(dev, offset);
reg &= ~(0xffffu << shift);
reg |= (uint32_t)value << shift;
pci_write32(dev, offset, reg);
}
void pci_write8(struct pci_device* dev, uint16_t offset, uint8_t value) {
uint32_t shift = (offset & 3) * 8;
uint32_t reg = pci_read32(dev, offset);
reg &= ~(0xffu << shift);
reg |= (uint32_t)value << shift;
pci_write32(dev, offset, reg);
}
errno_t pci_bar_get(struct pci_device* dev, size_t index, struct pci_bar* out) {
if (index >= PCI_NUM_BARS)
return EINVAL;
uint16_t bar_offset = PCI_BAR0 + index * sizeof(uint32_t);
uint16_t high_offset = bar_offset + sizeof(uint32_t);
uint32_t bar = pci_read32(dev, bar_offset);
bool is_mmio = (bar & 0x1) == 0;
bool is_mmio64 = is_mmio && ((bar >> 1) & 0x3) == 0x2;
bool is_prefetchable = is_mmio && (bar & (1 << 3));
bool is_64bit_pair = is_mmio64 && index + 1 < PCI_NUM_BARS;
uint16_t command = pci_read16(dev, PCI_COMMAND);
pci_write16(dev, PCI_COMMAND, command & ~(PCI_COMMAND_IO | PCI_COMMAND_MEM));
uint32_t high = is_64bit_pair ? pci_read32(dev, high_offset) : 0;
pci_write32(dev, bar_offset, 0xffff'ffff);
if (is_64bit_pair)
pci_write32(dev, high_offset, 0xffff'ffff);
uint32_t mask_low = pci_read32(dev, bar_offset);
uint32_t mask_high = is_64bit_pair ? pci_read32(dev, high_offset) : 0;
pci_write32(dev, bar_offset, bar);
if (is_64bit_pair)
pci_write32(dev, high_offset, high);
pci_write16(dev, PCI_COMMAND, command);
uint64_t addr_mask = is_mmio ? ~0xfull : ~0x3ull;
uint64_t raw = (uint64_t)mask_high << 32 | mask_low;
uint64_t masked = raw & addr_mask & (is_64bit_pair ? UINT64_MAX : UINT32_MAX);
struct pci_bar result = {
.size = masked == 0 ? 0 : (size_t)1 << __builtin_ctzll(masked),
.prefetchable = is_prefetchable,
};
if (is_mmio && is_64bit_pair) {
result.type = PCI_BAR_MMIO64;
result.address = (phys_t)high << 32 | (bar & 0xffff'fff0);
} else if (is_mmio) {
result.type = PCI_BAR_MMIO32;
result.address = bar & 0xffff'fff0;
} else {
result.type = PCI_BAR_IO;
result.address = (uint16_t)(bar & 0xffff'fffc);
}
if (result.address == 0)
return ENOENT;
*out = result;
return 0;
}
uint8_t pci_cap_next(struct pci_device* dev, uint8_t cur) {
uint8_t ptr;
if (cur == 0) {
if (!(pci_read16(dev, PCI_STATUS) & PCI_STATUS_CAP_LIST))
return 0;
ptr = pci_read8(dev, PCI_CAP_PTR) & ~3;
} else {
ptr = (pci_read32(dev, cur) >> 8) & ~3;
}
if (ptr == 0)
return 0;
if ((pci_read32(dev, ptr) & 0xff) == 0xff)
return 0;
return ptr;
}
uint8_t pci_cap_find(struct pci_device* dev, uint8_t id) {
for (uint8_t cap = pci_cap_next(dev, 0); cap != 0; cap = pci_cap_next(dev, cap)) {
if (pci_read8(dev, cap) == id)
return cap;
}
return 0;
}
static void pci_device_name(const struct pci_device* dev, char buf[static 18]) {
ksnprintf(buf, 18, "pci-" PCI_ADDR_FMT, PCI_ADDR_ARGS(&dev->address));
}
static bool scan_function(struct pci_access* access, struct pci_address addr) {
uint32_t reg0 = cfg_read32(access, &addr, PCI_VENDOR_ID);
uint16_t vendor_id = reg0;
uint16_t device_id = reg0 >> 16;
if (vendor_id == 0xffff || vendor_id == 0)
return false;
if (device_id == 0xffff || device_id == 0)
return false;
struct pci_device* dev = mem_alloc(sizeof(*dev), 0);
if (dev == nullptr) {
log_err("Out of memory while scanning " PCI_ADDR_FMT "\n", PCI_ADDR_ARGS(&addr));
return false;
}
dev->address = addr;
dev->access = access;
dev->id.vendor_id = vendor_id;
dev->id.device_id = device_id;
dev->class.prog_if = pci_read8(dev, PCI_PROG_IF);
dev->class.subclass = pci_read8(dev, PCI_SUBCLASS);
dev->class.class = pci_read8(dev, PCI_CLASS);
dev->header_type = pci_read8(dev, PCI_HEADER_TYPE);
if ((dev->header_type & PCI_HEADER_TYPE_MASK) == 0) {
dev->id.subvendor_id = pci_read16(dev, PCI_SUBSYS_VENDOR_ID);
dev->id.subdevice_id = pci_read16(dev, PCI_SUBSYS_ID);
}
pci_log(
dev,
"<id = %.4hx:%.4hx, class = %.2hhx:%.2hhx:%.2hhx>\n",
dev->id.vendor_id,
dev->id.device_id,
dev->class.class,
dev->class.subclass,
dev->class.prog_if
);
if (vec_push(&devices, dev) != 0) {
mem_free(dev);
return false;
}
return true;
}
static void scan_slot(struct pci_access* access, struct pci_address addr) {
if (!scan_function(access, addr))
return;
if (!(vec_elem_get(&devices, vec_length(&devices) - 1)->header_type & PCI_HEADER_TYPE_MULTIFUNCTION))
return;
for (addr.function = 1; addr.function < PCI_NUM_FUNCTIONS; addr.function++)
scan_function(access, addr);
}
static void format_match_id(char buf[static 5], uint16_t value) {
if (value == PCI_ANY_ID)
ksnprintf(buf, 5, "****");
else
ksnprintf(buf, 5, "%.4hx", value);
}
static void format_match_class(char buf[static 3], uint8_t value) {
if (value == PCI_ANY_CLASS)
ksnprintf(buf, 3, "**");
else
ksnprintf(buf, 3, "%.2hhx", value);
}
static void format_match(const struct pci_match* match, char* buf, size_t size) {
char vendor[5], device[5], class[3], subclass[3], prog_if[3];
format_match_id(vendor, match->vendor_id);
format_match_id(device, match->device_id);
format_match_class(class, match->class);
format_match_class(subclass, match->subclass);
format_match_class(prog_if, match->prog_if);
ksnprintf(buf, size, "<id = %s:%s, class = %s:%s:%s>", vendor, device, class, subclass, prog_if);
}
static bool pci_match_device(const struct pci_match* m, const struct pci_device* dev) {
return (m->vendor_id == PCI_ANY_ID || m->vendor_id == dev->id.vendor_id) &&
(m->device_id == PCI_ANY_ID || m->device_id == dev->id.device_id) &&
(m->class == PCI_ANY_CLASS || m->class == dev->class.class) &&
(m->subclass == PCI_ANY_CLASS || m->subclass == dev->class.subclass) &&
(m->prog_if == PCI_ANY_CLASS || m->prog_if == dev->class.prog_if);
}
// Returns the first entry that matches, or nullptr.
static const struct pci_match* pci_match_table(
const struct pci_match* table,
size_t num_matches,
const struct pci_device* dev
) {
for (size_t i = 0; i < num_matches; i++) {
if (pci_match_device(&table[i], dev))
return &table[i];
}
return nullptr;
}
errno_t pci_driver_register(struct pci_driver* driver) {
if (driver->match == nullptr || driver->num_matches == 0) {
log_warn("Driver \"%s\" does not define any matches, ignoring\n", driver->name);
return 0;
}
spin_lock(&device_lock);
vec_foreach(&drivers, i) {
if (strcmp(vec_elem_get(&drivers, i)->name, driver->name) == 0) {
spin_unlock(&device_lock);
log_warn("Driver \"%s\" is already registered\n", driver->name);
return EEXIST;
}
}
errno_t status = vec_push(&drivers, driver);
spin_unlock(&device_lock);
if (status != 0)
return status;
log("Registered PCI driver \"%s\" with %zu match%s\n",
driver->name,
driver->num_matches,
driver->num_matches == 1 ? "" : "es");
for (size_t i = 0; i < driver->num_matches; i++) {
char rule[48];
format_match(&driver->match[i], rule, sizeof(rule));
log(" [%zu] = %s\n", i, rule);
}
for (size_t i = 0;; i++) {
spin_lock(&device_lock);
if (i >= vec_length(&devices)) {
spin_unlock(&device_lock);
break;
}
struct pci_device* dev = vec_elem_get(&devices, i);
const struct pci_match* match = nullptr;
if (dev->driver == nullptr) {
match = pci_match_table(driver->match, driver->num_matches, dev);
if (match != nullptr)
dev->driver = driver;
}
spin_unlock(&device_lock);
if (match == nullptr)
continue;
pci_log(dev, "Matched driver \"%s\" on rule [%zu]\n", driver->name, (size_t)(match - driver->match));
status = driver->probe(dev, match);
if (status != 0) {
pci_log_warn(dev, "%s failed to probe: %i\n", driver->name, status);
spin_lock(&device_lock);
dev->driver = nullptr;
spin_unlock(&device_lock);
}
}
return 0;
}
[[__init]]
static void pci_stage_init(struct boot_info*) {
if (vec_is_empty(&accesses)) {
log_warn("No configuration space access method available\n");
return;
}
log("Scanning PCI devices\n");
spin_lock(&device_lock);
vec_foreach(&accesses, i) {
struct pci_access* access = vec_elem_get(&accesses, i);
for (uint32_t bus = access->start_bus; bus <= access->end_bus; bus++) {
for (uint8_t slot = 0; slot < PCI_NUM_SLOTS; slot++) {
struct pci_address addr = {
.domain = access->domain,
.bus = bus,
.device = slot,
};
if (pci_access_find(&addr) != access)
continue;
scan_slot(access, addr);
}
}
}
spin_unlock(&device_lock);
log("Found %zu device(s)\n", vec_length(&devices));
}
INIT_TASK(pci_stage, "dev.pci", pci_stage_init);
INIT_DEPENDS(pci_stage, mem_stage);
-76
View File
@@ -1,76 +0,0 @@
#define pr_fmt(fmt) "pci: " fmt
#include <zinnia/alloc.h>
#include <zinnia/mmio.h>
#include <zinnia/pci.h>
#include <zinnia/pmap.h>
#include <zinnia/print.h>
#include <zinnia/utils.h>
#include <zinnia/virt.h>
#include <zinnia/vma.h>
#include <arch/mem.h>
struct pci_ecam {
struct pci_access access;
void* base;
};
static void* ecam_ptr(struct pci_access* self, const struct pci_address* addr, uint16_t offset) {
struct pci_ecam* ecam = containerof(self, struct pci_ecam, access);
size_t index = (size_t)(addr->bus - self->start_bus) << 20 | (size_t)(addr->device & 0x1f) << 15 |
(size_t)(addr->function & 0x7) << 12 | (offset & 0xffc);
return (uint8_t*)ecam->base + index;
}
static uint32_t ecam_read32(struct pci_access* self, const struct pci_address* addr, uint16_t offset) {
return mmio_read32(ecam_ptr(self, addr, offset));
}
static void ecam_write32(struct pci_access* self, const struct pci_address* addr, uint16_t offset, uint32_t value) {
mmio_write32(ecam_ptr(self, addr, offset), value);
}
errno_t pci_ecam_register(phys_t base, uint16_t domain, uint8_t start_bus, uint8_t end_bus) {
if (end_bus < start_bus)
return EINVAL;
size_t length = ((size_t)(end_bus - start_bus) + 1) << 20;
phys_t phys = base + ((phys_t)start_bus << 20);
uintptr_t vaddr = vm_alloc(length);
if (!vaddr)
return ENOMEM;
for (size_t i = 0; i < length; i += arch_mem_page_size()) {
errno_t status = pmap_map(&kernel_vma.pmap, vaddr + i, phys + i, PTE_READ | PTE_WRITE, CACHE_MMIO);
if (status != 0)
return status;
}
struct pci_ecam* ecam = mem_alloc(sizeof(*ecam), 0);
if (ecam == nullptr)
return ENOMEM;
*ecam = (struct pci_ecam){
.access =
{
.name = "ecam",
.domain = domain,
.start_bus = start_bus,
.end_bus = end_bus,
.priority = PCI_ACCESS_PRIO_ECAM,
.read32 = ecam_read32,
.write32 = ecam_write32,
},
.base = (void*)vaddr,
};
errno_t status = pci_access_register(&ecam->access);
if (status != 0) {
mem_free(ecam);
return status;
}
log("ECAM for %.4hx:%.2hhx - %.4hx:%.2hhx at %p\n", domain, start_bus, domain, end_bus, (void*)phys);
return 0;
}
-4
View File
@@ -1,4 +0,0 @@
kernel_sources += files(
'core.c',
'ecam.c',
)
-9
View File
@@ -1,9 +0,0 @@
menu "Video Drivers"
config FBCON
bool "Framebuffer console"
default y
help
Adds a basic console that can draw on a framebuffer passed by firmware.
endmenu
-205
View File
@@ -1,205 +0,0 @@
#include <zinnia/alloc.h>
#include <zinnia/assert.h>
#include <zinnia/console.h>
#include <zinnia/init.h>
#include <zinnia/pmap.h>
#include <zinnia/sched.h>
#include <zinnia/utils.h>
#include <zinnia/vma.h>
#include <stdint.h>
#include <string.h>
static const uint8_t fbcon_font[] = {
#embed "fbcon_font.bin"
};
constexpr size_t FONT_WIDTH = 8;
constexpr size_t FONT_HEIGHT = 12;
constexpr uint32_t FG_COLOR = 0xaaaaaa;
constexpr uint32_t BG_COLOR = 0x000000;
enum esc_state {
ESC_NONE,
ESC_START,
ESC_CSI,
};
static struct {
struct boot_framebuffer fb;
uint32_t* back;
uint32_t fg, bg;
size_t cols, rows;
size_t offset_x, offset_y;
size_t cx, cy;
enum esc_state esc;
} fbcon;
static inline uint8_t* fb_ptr() {
return HHDM_PTR(fbcon.fb.base);
}
static inline uint32_t* back_row(size_t y) {
return fbcon.back + y * fbcon.fb.width;
}
static void flush_rect(size_t x, size_t y, size_t w, size_t h) {
for (size_t j = 0; j < h; j++)
memcpy((uint32_t*)(fb_ptr() + (y + j) * fbcon.fb.pitch) + x, back_row(y + j) + x, w * sizeof(uint32_t));
}
static uint32_t pack_color(uint32_t rgb) {
const struct boot_framebuffer* fb = &fbcon.fb;
uint32_t r = (rgb >> 16) & 0xff;
uint32_t g = (rgb >> 8) & 0xff;
uint32_t b = rgb & 0xff;
return ((r >> (8 - fb->red.size)) << fb->red.shift) | ((g >> (8 - fb->green.size)) << fb->green.shift) |
((b >> (8 - fb->blue.size)) << fb->blue.shift);
}
static void fill_rect(size_t x, size_t y, size_t w, size_t h, uint32_t color) {
for (size_t j = 0; j < h; j++) {
uint32_t* row = back_row(y + j) + x;
for (size_t i = 0; i < w; i++)
row[i] = color;
}
flush_rect(x, y, w, h);
}
static void clear_screen() {
fill_rect(0, 0, fbcon.fb.width, fbcon.fb.height, fbcon.bg);
fbcon.cx = fbcon.cy = 0;
}
static void draw_glyph(size_t col, size_t row, uint8_t ch) {
const uint8_t* glyph = &fbcon_font[ch * FONT_HEIGHT];
size_t x = fbcon.offset_x + col * FONT_WIDTH;
size_t y = fbcon.offset_y + row * FONT_HEIGHT;
for (size_t j = 0; j < FONT_HEIGHT; j++) {
uint32_t* line = back_row(y + j) + x;
for (size_t i = 0; i < FONT_WIDTH; i++)
line[i] = (glyph[j] & (0x80 >> i)) ? fbcon.fg : fbcon.bg;
}
flush_rect(x, y, FONT_WIDTH, FONT_HEIGHT);
}
static void scroll_up() {
const size_t width = fbcon.fb.width;
const size_t text_y = fbcon.offset_y;
const size_t text_h = fbcon.rows * FONT_HEIGHT;
memmove(back_row(text_y), back_row(text_y + FONT_HEIGHT), (text_h - FONT_HEIGHT) * width * sizeof(uint32_t));
for (size_t j = text_y + text_h - FONT_HEIGHT; j < text_y + text_h; j++) {
uint32_t* row = back_row(j);
for (size_t i = 0; i < width; i++)
row[i] = fbcon.bg;
}
flush_rect(0, text_y, width, text_h);
}
static void newline() {
fbcon.cx = 0;
if (++fbcon.cy >= fbcon.rows) {
fbcon.cy = fbcon.rows - 1;
scroll_up();
}
}
static void put_char(uint8_t ch) {
switch (fbcon.esc) {
case ESC_START:
fbcon.esc = ch == '[' ? ESC_CSI : ESC_NONE;
if (ch == 'c')
clear_screen();
return;
case ESC_CSI:
if (ch >= 0x40 && ch <= 0x7e)
fbcon.esc = ESC_NONE;
return;
case ESC_NONE:
break;
}
switch (ch) {
case 0x1b:
fbcon.esc = ESC_START;
break;
case '\n':
newline();
break;
case '\r':
fbcon.cx = 0;
break;
case '\b':
if (fbcon.cx > 0)
fbcon.cx--;
break;
case '\t':
fbcon.cx = (fbcon.cx + 8) & ~(size_t)7;
if (fbcon.cx >= fbcon.cols)
newline();
break;
default:
if (fbcon.cx >= fbcon.cols)
newline();
draw_glyph(fbcon.cx++, fbcon.cy, ch);
break;
}
}
static void fbcon_write(struct console* con, const char* buf, size_t count) {
for (size_t i = 0; i < count; i++)
put_char((uint8_t)buf[i]);
}
static bool fbcon_setup(struct console* con) {
const struct boot_framebuffer* fb = &fbcon.fb;
if (fb->bytes_per_pixel != 4 || fb->red.size > 8 || fb->green.size > 8 || fb->blue.size > 8)
return false;
fbcon.fg = pack_color(FG_COLOR);
fbcon.bg = pack_color(BG_COLOR);
fbcon.cols = fb->width / FONT_WIDTH;
fbcon.rows = fb->height / FONT_HEIGHT;
fbcon.offset_x = (fb->width % FONT_WIDTH) / 2;
fbcon.offset_y = (fb->height % FONT_HEIGHT) / 2;
if (!fbcon.cols || !fbcon.rows)
return false;
clear_screen();
return true;
}
static struct console fbcon_con = {
.name = "fbcon",
.init = fbcon_setup,
.write = fbcon_write,
};
[[__init]]
void fbcon_init(struct boot_info* info) {
const struct boot_framebuffer* fb = &info->fb;
if (!fb->base)
return;
fbcon.fb = *fb;
const size_t pgsz = arch_mem_page_size();
const phys_t start = ALIGN_DOWN(fb->base, pgsz);
const phys_t end = ALIGN_UP(fb->base + fb->pitch * fb->height, pgsz);
for (phys_t p = start; p < end; p += pgsz) {
errno_t status =
pmap_map(&kernel_vma.pmap, (uintptr_t)HHDM_PTR(p), p, PTE_READ | PTE_WRITE, CACHE_WRITE_COMBINE);
if (status)
return;
}
fbcon.back = mem_alloc(fb->width * fb->height * sizeof(uint32_t), ALLOC_NOZERO);
if (!fbcon.back)
return;
console_register(&fbcon_con);
}
INIT_TASK(fbcon_stage, "core.fbcon", fbcon_init);
INIT_DEPENDS(fbcon_stage, sched_stage);
Binary file not shown.
-1
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@@ -1 +0,0 @@
kernel_sources += files('fbcon.c')
-3
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@@ -1,3 +0,0 @@
if kconfig.get('CONFIG_FBCON', 'n') == 'y'
subdir('fbcon')
endif
-3
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@@ -1,3 +0,0 @@
kernel_sources += files(
'elf.c',
)
-1
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@@ -1 +0,0 @@
subdir('exec')
-17
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@@ -1,17 +0,0 @@
#include <zinnia/ident.h>
static const struct ident kernel_identity = {0};
const struct ident* ident_kernel() {
return &kernel_identity;
}
bool ident_in_group(const struct ident* identity, gid_t gid, bool use_real) {
if (gid == (use_real ? identity->gid : identity->egid))
return true;
vec_foreach(&identity->groups, i) {
if (vec_elem_get(&identity->groups, i) == gid)
return true;
}
return false;
}
-3
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@@ -1,3 +0,0 @@
#include <zinnia/vfs.h>
void vfs_init() {}
-4
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@@ -1,4 +0,0 @@
kernel_sources += files(
'ident.c',
'init.c',
)
-8
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@@ -1,8 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#include <zinnia/errno.h>
#include <stdint.h>
struct syscall_ret arch_archctl(uintptr_t op, uintptr_t value);
-5
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@@ -1,5 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#include <bits/cpu.h>
-5
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@@ -1,5 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
// TODO: Ensure bits are defining values right.
-10
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@@ -1,10 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#include <zinnia/irq.h>
bool arch_irq_set_state(bool state);
bool arch_irq_get_state();
void arch_irq_wait();
errno_t arch_irq_alloc_msi(struct msi_line** out);
-31
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@@ -1,31 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#include <zinnia/compiler.h>
#include <stddef.h>
#include <stdint.h>
[[__pure]]
bool arch_mem_addr_is_user(uintptr_t addr);
[[__pure]]
size_t arch_mem_page_size();
[[__pure]]
size_t arch_mem_page_bits();
[[__pure]]
size_t arch_mem_level_bits();
[[__pure]]
size_t arch_mem_num_levels();
[[__pure]]
uintptr_t arch_mem_hhdm_addr();
[[__pure]]
uintptr_t arch_mem_pfndb_addr();
[[__pure]]
uintptr_t arch_mem_mapping_addr();
-9
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@@ -1,9 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#include <zinnia/percpu.h>
struct percpu* arch_percpu_get();
void arch_percpu_bsp_init();
void arch_percpu_init();
-27
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@@ -1,27 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#include <zinnia/errno.h>
#include <zinnia/sched.h>
struct percpu;
void arch_sched_preempt_disable();
bool arch_sched_preempt_enable();
void arch_sched_kick(struct percpu* cpu);
struct task* arch_sched_switch(struct task* from, struct task* to);
errno_t arch_task_init(
struct arch_task_context* context,
void* entry,
uintptr_t arg0,
uintptr_t stack_start,
bool is_user
);
void arch_task_fini(struct arch_task_context* context);
void arch_task_fork(struct arch_task_context* dst);
void arch_context_init_user(struct arch_context* ctx, uintptr_t ip, uintptr_t sp);
[[noreturn]]
void arch_sched_jump_to_context(struct arch_context* context);
[[noreturn]]
void arch_sched_jump_to_user(uintptr_t ip, uintptr_t sp, uintptr_t arg);
-7
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@@ -1,7 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#include <stdint.h>
void arch_timer_program(uint64_t deadline_ns);
-12
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@@ -1,12 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#include <zinnia/compiler.h>
#include <zinnia/usercopy.h>
#include <stddef.h>
void arch_usercopy_allow(bool state);
bool arch_usercopy_read(void* dst, const __user void* src, size_t len, struct usercopy_region** region);
bool arch_usercopy_write(__user void* dst, const void* src, size_t len, struct usercopy_region** region);
bool arch_usercopy_strlen(const __user char* str, size_t max, size_t* len, struct usercopy_region** region);
@@ -1,4 +1,4 @@
// SPDX-License-Identifier: ISC
// SPDX-License-Identifier: MIT
#pragma once
@@ -6,7 +6,6 @@
#define __section(x) gnu::section(x)
#define __aligned(x) gnu::aligned(x)
#define __packed gnu::packed
#define __may_alias gnu::may_alias
#define __naked gnu::naked
// These hints may improve code generation.
@@ -15,12 +14,11 @@
#define __used gnu::used
#define __unused gnu::unused
#define __format(like, ...) gnu::format(like, __VA_ARGS__)
#define __force_inline gnu::always_inline
#define __visibility gnu::visibility
#define __pure gnu::pure
#define __likely(x) __builtin_expect(!!(x), 1)
#define __unlikely(x) __builtin_expect(!!(x), 0)
// Only clang has these hints, GCC would throw a warning here.
// clang::noderef also doesn't support the C23 attribute format.
// Only clang has these hints, GCC will throw a warning here.
// They also don't support the C23 attribute format.
#ifdef __clang__
#define __user __attribute__((noderef, address_space(1)))
#define __phys __attribute__((noderef, address_space(2)))
@@ -28,6 +26,3 @@
#define __user
#define __phys
#endif
#define __likely(x) __builtin_expect(!!(x), 1)
#define __unlikely(x) __builtin_expect(!!(x), 0)
+69 -59
View File
@@ -1,10 +1,7 @@
// SPDX-License-Identifier: ISC
// SPDX-License-Identifier: MIT
#pragma once
#include <zinnia/errno.h>
#include <zinnia/vfs.h>
#include <arch/elf.h>
#include <stdint.h>
constexpr char ELF_MAG[4] = {0x7F, 'E', 'L', 'F'};
@@ -76,20 +73,6 @@ enum : uint32_t {
PT_TLS = 0x00000007,
};
enum : uint32_t {
PT_MOD_VERSION = 0x60000001,
PT_MOD_AUTHOR = 0x60000002,
PT_MOD_DESC = 0x60000003,
PT_MOD_LICENSE = 0x60000004,
PT_MOD_CMDLINE = 0x60000005,
PT_MOD_EXIT = 0x60000006,
PT_MOD_MATCH = 0x60000007,
};
enum : uint16_t {
SHN_UNDEF = 0,
};
enum : uint32_t {
PF_X = 0x00000001,
PF_W = 0x00000002,
@@ -126,9 +109,6 @@ enum : uint32_t {
DT_FINI_ARRAY = 26,
DT_INIT_ARRAYSZ = 27,
DT_FINI_ARRAYSZ = 28,
DT_RELRSZ = 35,
DT_RELR = 36,
DT_RELRENT = 37,
DT_LOOS = 0x60000000,
DT_HIOS = 0x6FFFFFFF,
DT_LOPROC = 0x70000000,
@@ -159,7 +139,7 @@ enum : uint32_t {
AT_INIT_HANDLE = 0x1000,
};
typedef struct {
struct elf64_ehdr {
uint8_t e_ident[EI_NIDENT];
uint16_t e_type;
uint16_t e_machine;
@@ -174,9 +154,9 @@ typedef struct {
uint16_t e_shentsize;
uint16_t e_shnum;
uint16_t e_shstrndx;
} elf64_ehdr_t;
};
typedef struct {
struct elf32_ehdr {
uint8_t e_ident[EI_NIDENT];
uint16_t e_type;
uint16_t e_machine;
@@ -191,9 +171,9 @@ typedef struct {
uint16_t e_shentsize;
uint16_t e_shnum;
uint16_t e_shstrndx;
} elf32_ehdr_t;
};
typedef struct {
struct elf64_phdr {
uint32_t p_type;
uint32_t p_flags;
elf64_off_t p_offset;
@@ -202,9 +182,9 @@ typedef struct {
uint64_t p_filesz;
uint64_t p_memsz;
uint64_t p_align;
} elf64_phdr_t;
};
typedef struct {
struct elf32_phdr {
uint32_t p_type;
elf32_off_t p_offset;
elf32_addr_t p_vaddr;
@@ -213,68 +193,68 @@ typedef struct {
uint32_t p_memsz;
uint32_t p_flags;
uint32_t p_align;
} elf32_phdr_t;
};
typedef struct {
struct elf64_dyn {
int64_t d_tag;
union {
uint64_t d_val;
elf64_addr_t d_ptr;
} d_un;
} elf64_dyn_t;
};
typedef struct {
struct elf32_dyn {
int32_t r_offset;
union {
uint32_t d_val;
elf32_addr_t d_ptr;
} d_un;
} elf32_dyn_t;
};
typedef struct {
struct elf64_nhdr {
uint64_t n_namesz;
uint64_t n_descsz;
uint64_t n_type;
} elf64_nhdr_t;
};
typedef struct {
struct elf32_nhdr {
uint32_t n_namesz;
uint32_t n_descsz;
uint32_t n_type;
} elf32_nhdr_t;
};
typedef struct {
struct elf64_auxv {
uint64_t atype;
uint64_t avalue;
} elf64_auxv_t;
};
typedef struct {
struct elf32_auxv {
uint32_t atype;
uint32_t avalue;
} elf32_auxv_t;
};
typedef struct {
struct elf_hash {
uint32_t n_buckets;
uint32_t n_chain;
} elf_hash_t;
};
typedef struct {
struct elf32_sym {
elf32_off_t st_name;
elf32_addr_t st_value;
elf32_off_t st_size;
uint8_t st_info;
uint8_t st_other;
uint16_t st_shndx;
} elf32_sym_t;
};
typedef struct {
struct elf64_sym {
uint32_t st_name;
uint8_t st_info;
uint8_t st_other;
uint16_t st_shndx;
uint64_t st_value;
uint64_t st_size;
} elf64_sym_t;
};
static uint8_t ELF64_ST_BIND(uint8_t info) {
return info >> 4;
@@ -291,7 +271,7 @@ static inline uint8_t ELF64_ST_INFO(uint8_t bind, uint8_t type) {
typedef struct {
uint16_t si_boundto;
uint16_t si_flags;
} elf64_syminfo_t;
} elf64_syminfo;
static inline uint8_t ELF32_ST_BIND(uint8_t info) {
return info >> 4;
@@ -323,30 +303,27 @@ enum {
STT_HIPROC = 15
};
typedef struct {
struct elf32_rela {
elf32_addr_t r_offset;
uint32_t r_info;
int32_t r_addend;
} elf32_rela_t;
};
typedef struct {
struct elf64_rela {
elf64_addr_t r_offset;
uint64_t r_info;
int64_t r_addend;
} elf64_rela_t;
};
typedef uint64_t elf64_relr_t;
typedef uint32_t elf32_relr_t;
typedef struct {
struct elf32_rel {
elf32_addr_t r_offset;
uint32_t r_info;
} elf32_rel_t;
};
typedef struct {
struct elf64_rel {
elf64_addr_t r_offset;
uint64_t r_info;
} elf64_rel_t;
};
static inline uint32_t ELF32_R_SYM(uint32_t info) {
return info >> 8;
@@ -363,3 +340,36 @@ static inline uint32_t ELF64_R_SYM(uint64_t info) {
static inline uint32_t ELF64_R_TYPE(uint64_t info) {
return info & 0xFFFFFFFF;
}
// Architecture specific bits.
#ifdef __x86_64__
#define ELF_ARCH_CLASS ELFCLASS64
#define ELF_ARCH_DATA ELFDATA2LSB
#define ELF_ARCH_MACHINE EM_X86_64
#define ELF_R_SYM ELF64_R_SYM
#define ELF_R_TYPE ELF64_R_TYPE
#define ELF_ST_BIND ELF64_ST_BIND
#define ELF_ST_TYPE ELF64_ST_TYPE
#define elf_ehdr elf64_ehdr
#define elf_phdr elf64_phdr
#define elf_dyn elf64_dyn
#define elf_addr elf64_addr
#define elf_off elf64_off
#define elf_nhdr elf64_nhdr
#define elf_auxv elf64_auxv
#define elf_sym elf64_sym
#define elf_rela elf64_rela
#define elf_rel elf64_rel
enum {
R_NONE = 0,
R_COPY = 5,
R_GLOB_DAT = 6,
R_JUMP_SLOT = 7,
R_RELATIVE = 8,
R_IRELATIVE = 37,
};
#endif
@@ -1,4 +1,4 @@
// SPDX-License-Identifier: ISC
// SPDX-License-Identifier: MIT
#pragma once
@@ -22,13 +22,13 @@
__builtin_types_compatible_p(typeof(*(ptr)), typeof(((type*)0)->member)), \
"Incompatible types for containerof" \
); \
(type*)((size_t)(ptr) - offsetof(type, member)); \
(type*)((size_t)ptr - offsetof(type, member)); \
})
#endif
#endif
#ifndef containerof
// Get pointer to parent object given pointer to a struct or union member.
#define containerof(ptr, type, member) (type*)((size_t)(ptr) - offsetof(type, member))
#define containerof(ptr, type, member) (type*)((size_t)ptr - offsetof(type, member))
#endif
#define CONCAT(A, B) _CONCAT(A, B)
+36
View File
@@ -0,0 +1,36 @@
#pragma once
#include <zinnia/channel.h>
#include <zinnia/handle.h>
#include <common/utils.h>
#include <stdint.h>
#define ZN_IPC_NUM(group, num) ((uint32_t)(group) << 24u) | ((uint32_t)(num) & 0xffffffu)
#define ZN_IPC(name, group, num, num_handles) \
name##_inner; \
constexpr uint32_t name##_num = ZN_IPC_NUM(group, num); \
typedef struct { \
uint32_t id; \
zn_handle_t handles[num_handles]; \
name##_inner inner; \
} name
#define zn_ipc_write(channel, obj) \
zn_channel_write(channel, (obj)->handles, &(obj)->inner, ARRAY_SIZE((obj)->handles), sizeof((obj)->inner))
#define zn_ipc_read(channel, obj) \
zn_channel_read( \
channel, \
(obj)->handles, \
&(obj)->inner, \
ARRAY_SIZE((obj)->handles), \
sizeof((obj)->inner), \
nullptr, \
nullptr \
)
#define zn_ipc_new(name) \
(zn_ipc_fw_rsdp) { \
.id = name##_num \
}
-16
View File
@@ -1,16 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
typedef __builtin_va_list va_list;
#undef va_start
#define va_start(v, ...) __builtin_va_start(v, 0)
#undef va_end
#define va_end(v) __builtin_va_end(v)
#undef va_arg
#define va_arg(v, l) __builtin_va_arg(v, l)
#undef va_copy
#define va_copy(d, s) __builtin_va_copy(d, s)
-6
View File
@@ -1,6 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#define ckd_add(result, a, b) __builtin_add_overflow(a, b, result)
#define ckd_sub(result, a, b) __builtin_sub_overflow(a, b, result)
#define ckd_mul(result, a, b) __builtin_mul_overflow(a, b, result)
-14
View File
@@ -1,14 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
typedef __SIZE_TYPE__ size_t;
typedef __PTRDIFF_TYPE__ ptrdiff_t;
typedef __WCHAR_TYPE__ wchar_t;
typedef typeof(nullptr) nullptr_t;
#undef offsetof
#define offsetof(s, m) __builtin_offsetof(s, m)
#undef unreachable
#define unreachable() __builtin_unreachable()
-354
View File
@@ -1,354 +0,0 @@
// SPDX-License-Identifier: ISC
#pragma once
#ifdef __UINT8_TYPE__
typedef __UINT8_TYPE__ uint8_t;
#endif
#ifdef __UINT16_TYPE__
typedef __UINT16_TYPE__ uint16_t;
#endif
#ifdef __UINT32_TYPE__
typedef __UINT32_TYPE__ uint32_t;
#endif
#ifdef __UINT64_TYPE__
typedef __UINT64_TYPE__ uint64_t;
#endif
typedef __UINT_LEAST8_TYPE__ uint_least8_t;
typedef __UINT_LEAST16_TYPE__ uint_least16_t;
typedef __UINT_LEAST32_TYPE__ uint_least32_t;
typedef __UINT_LEAST64_TYPE__ uint_least64_t;
typedef __UINT_FAST8_TYPE__ uint_fast8_t;
typedef __UINT_FAST16_TYPE__ uint_fast16_t;
typedef __UINT_FAST32_TYPE__ uint_fast32_t;
typedef __UINT_FAST64_TYPE__ uint_fast64_t;
#ifdef __INT8_TYPE__
typedef __INT8_TYPE__ int8_t;
#endif
#ifdef __INT16_TYPE__
typedef __INT16_TYPE__ int16_t;
#endif
#ifdef __INT32_TYPE__
typedef __INT32_TYPE__ int32_t;
#endif
#ifdef __INT64_TYPE__
typedef __INT64_TYPE__ int64_t;
#endif
typedef __INT_LEAST8_TYPE__ int_least8_t;
typedef __INT_LEAST16_TYPE__ int_least16_t;
typedef __INT_LEAST32_TYPE__ int_least32_t;
typedef __INT_LEAST64_TYPE__ int_least64_t;
typedef __INT_FAST8_TYPE__ int_fast8_t;
typedef __INT_FAST16_TYPE__ int_fast16_t;
typedef __INT_FAST32_TYPE__ int_fast32_t;
typedef __INT_FAST64_TYPE__ int_fast64_t;
#ifdef __UINTPTR_TYPE__
typedef __UINTPTR_TYPE__ uintptr_t;
#endif
#ifdef __INTPTR_TYPE__
typedef __INTPTR_TYPE__ intptr_t;
#endif
typedef __UINTMAX_TYPE__ uintmax_t;
typedef __INTMAX_TYPE__ intmax_t;
// Clang and GCC have different mechanisms for INT32_C and friends.
#ifdef __clang__
#ifndef __FREESTANDING_C_HDRS_C_JOIN
#define __FREESTANDING_C_HDRS_C_EXPAND_JOIN(x, suffix) x##suffix
#define __FREESTANDING_C_HDRS_C_JOIN(x, suffix) __FREESTANDING_C_HDRS_C_EXPAND_JOIN(x, suffix)
#endif
#undef INT8_C
#define INT8_C(x) __FREESTANDING_C_HDRS_C_JOIN(x, __INT8_C_SUFFIX__)
#undef INT16_C
#define INT16_C(x) __FREESTANDING_C_HDRS_C_JOIN(x, __INT16_C_SUFFIX__)
#undef INT32_C
#define INT32_C(x) __FREESTANDING_C_HDRS_C_JOIN(x, __INT32_C_SUFFIX__)
#undef INT64_C
#define INT64_C(x) __FREESTANDING_C_HDRS_C_JOIN(x, __INT64_C_SUFFIX__)
#undef UINT8_C
#define UINT8_C(x) __FREESTANDING_C_HDRS_C_JOIN(x, __UINT8_C_SUFFIX__)
#undef UINT16_C
#define UINT16_C(x) __FREESTANDING_C_HDRS_C_JOIN(x, __UINT16_C_SUFFIX__)
#undef UINT32_C
#define UINT32_C(x) __FREESTANDING_C_HDRS_C_JOIN(x, __UINT32_C_SUFFIX__)
#undef UINT64_C
#define UINT64_C(x) __FREESTANDING_C_HDRS_C_JOIN(x, __UINT64_C_SUFFIX__)
#undef INTMAX_C
#define INTMAX_C(x) __FREESTANDING_C_HDRS_C_JOIN(x, __INTMAX_C_SUFFIX__)
#undef UINTMAX_C
#define UINTMAX_C(x) __FREESTANDING_C_HDRS_C_JOIN(x, __UINTMAX_C_SUFFIX__)
#else
#undef INT8_C
#define INT8_C(x) __INT8_C(x)
#undef INT16_C
#define INT16_C(x) __INT16_C(x)
#undef INT32_C
#define INT32_C(x) __INT32_C(x)
#undef INT64_C
#define INT64_C(x) __INT64_C(x)
#undef UINT8_C
#define UINT8_C(x) __UINT8_C(x)
#undef UINT16_C
#define UINT16_C(x) __UINT16_C(x)
#undef UINT32_C
#define UINT32_C(x) __UINT32_C(x)
#undef UINT64_C
#define UINT64_C(x) __UINT64_C(x)
#undef INTMAX_C
#define INTMAX_C(x) __INTMAX_C(x)
#undef UINTMAX_C
#define UINTMAX_C(x) __UINTMAX_C(x)
#endif
#ifdef __UINT8_MAX__
#undef UINT8_MAX
#define UINT8_MAX __UINT8_MAX__
#endif
#ifdef __UINT16_MAX__
#undef UINT16_MAX
#define UINT16_MAX __UINT16_MAX__
#endif
#ifdef __UINT32_MAX__
#undef UINT32_MAX
#define UINT32_MAX __UINT32_MAX__
#endif
#ifdef __UINT64_MAX__
#undef UINT64_MAX
#define UINT64_MAX __UINT64_MAX__
#endif
#ifdef __INT8_MAX__
#undef INT8_MAX
#define INT8_MAX __INT8_MAX__
#endif
#ifdef __INT16_MAX__
#undef INT16_MAX
#define INT16_MAX __INT16_MAX__
#endif
#ifdef __INT32_MAX__
#undef INT32_MAX
#define INT32_MAX __INT32_MAX__
#endif
#ifdef __INT64_MAX__
#undef INT64_MAX
#define INT64_MAX __INT64_MAX__
#endif
#ifdef __INT8_MAX__
#undef INT8_MIN
#define INT8_MIN (-INT8_MAX - 1)
#endif
#ifdef __INT16_MAX__
#undef INT16_MIN
#define INT16_MIN (-INT16_MAX - 1)
#endif
#ifdef __INT32_MAX__
#undef INT32_MIN
#define INT32_MIN (-INT32_MAX - 1)
#endif
#ifdef __INT64_MAX__
#undef INT64_MIN
#define INT64_MIN (-INT64_MAX - 1)
#endif
#undef UINT_LEAST8_MAX
#define UINT_LEAST8_MAX __UINT_LEAST8_MAX__
#undef UINT_LEAST16_MAX
#define UINT_LEAST16_MAX __UINT_LEAST16_MAX__
#undef UINT_LEAST32_MAX
#define UINT_LEAST32_MAX __UINT_LEAST32_MAX__
#undef UINT_LEAST64_MAX
#define UINT_LEAST64_MAX __UINT_LEAST64_MAX__
#undef INT_LEAST8_MAX
#define INT_LEAST8_MAX __INT_LEAST8_MAX__
#undef INT_LEAST16_MAX
#define INT_LEAST16_MAX __INT_LEAST16_MAX__
#undef INT_LEAST32_MAX
#define INT_LEAST32_MAX __INT_LEAST32_MAX__
#undef INT_LEAST64_MAX
#define INT_LEAST64_MAX __INT_LEAST64_MAX__
#undef INT_LEAST8_MIN
#define INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)
#undef INT_LEAST16_MIN
#define INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)
#undef INT_LEAST32_MIN
#define INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)
#undef INT_LEAST64_MIN
#define INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)
#undef UINT_FAST8_MAX
#define UINT_FAST8_MAX __UINT_FAST8_MAX__
#undef UINT_FAST16_MAX
#define UINT_FAST16_MAX __UINT_FAST16_MAX__
#undef UINT_FAST32_MAX
#define UINT_FAST32_MAX __UINT_FAST32_MAX__
#undef UINT_FAST64_MAX
#define UINT_FAST64_MAX __UINT_FAST64_MAX__
#undef INT_FAST8_MAX
#define INT_FAST8_MAX __INT_FAST8_MAX__
#undef INT_FAST16_MAX
#define INT_FAST16_MAX __INT_FAST16_MAX__
#undef INT_FAST32_MAX
#define INT_FAST32_MAX __INT_FAST32_MAX__
#undef INT_FAST64_MAX
#define INT_FAST64_MAX __INT_FAST64_MAX__
#undef INT_FAST8_MIN
#define INT_FAST8_MIN (-INT_FAST8_MAX - 1)
#undef INT_FAST16_MIN
#define INT_FAST16_MIN (-INT_FAST16_MAX - 1)
#undef INT_FAST32_MIN
#define INT_FAST32_MIN (-INT_FAST32_MAX - 1)
#undef INT_FAST64_MIN
#define INT_FAST64_MIN (-INT_FAST64_MAX - 1)
#ifdef __UINTPTR_MAX__
#undef UINTPTR_MAX
#define UINTPTR_MAX __UINTPTR_MAX__
#endif
#ifdef __INTPTR_MAX__
#undef INTPTR_MAX
#define INTPTR_MAX __INTPTR_MAX__
#undef INTPTR_MIN
#define INTPTR_MIN (-INTPTR_MAX - 1)
#endif
#undef UINTMAX_MAX
#define UINTMAX_MAX __UINTMAX_MAX__
#undef INTMAX_MAX
#define INTMAX_MAX __INTMAX_MAX__
#undef INTMAX_MIN
#define INTMAX_MIN (-INTMAX_MAX - 1)
#undef PTRDIFF_MAX
#define PTRDIFF_MAX __PTRDIFF_MAX__
#undef PTRDIFF_MIN
#define PTRDIFF_MIN (-PTRDIFF_MAX - 1)
#undef SIG_ATOMIC_MAX
#define SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__
#undef SIG_ATOMIC_MIN
#define SIG_ATOMIC_MIN (-SIG_ATOMIC_MAX - 1)
#undef SIZE_MAX
#define SIZE_MAX __SIZE_MAX__
#undef WCHAR_MAX
#define WCHAR_MAX __WCHAR_MAX__
#undef WCHAR_MIN
#define WCHAR_MIN (-WCHAR_MAX - 1)
#undef WINT_MAX
#define WINT_MAX __WINT_MAX__
#undef WINT_MIN
#define WINT_MIN (-WINT_MAX - 1)
#ifdef __INT8_TYPE__
#undef INT8_WIDTH
#define INT8_WIDTH 8
#endif
#ifdef __UINT8_TYPE__
#undef UINT8_WIDTH
#define UINT8_WIDTH 8
#endif
#ifdef __INT16_TYPE__
#undef INT16_WIDTH
#define INT16_WIDTH 16
#endif
#ifdef __UINT16_TYPE__
#undef UINT16_WIDTH
#define UINT16_WIDTH 16
#endif
#ifdef __INT32_TYPE__
#undef INT32_WIDTH
#define INT32_WIDTH 32
#endif
#ifdef __UINT32_TYPE__
#undef UINT32_WIDTH
#define UINT32_WIDTH 32
#endif
#ifdef __INT64_TYPE__
#undef INT64_WIDTH
#define INT64_WIDTH 64
#endif
#ifdef __UINT64_TYPE__
#undef UINT64_WIDTH
#define UINT64_WIDTH 64
#endif
#undef INT_LEAST8_WIDTH
#define INT_LEAST8_WIDTH __INT_LEAST8_WIDTH__
#undef UINT_LEAST8_WIDTH
#define UINT_LEAST8_WIDTH __INT_LEAST8_WIDTH__
#undef INT_LEAST16_WIDTH
#define INT_LEAST16_WIDTH __INT_LEAST16_WIDTH__
#undef UINT_LEAST16_WIDTH
#define UINT_LEAST16_WIDTH __INT_LEAST16_WIDTH__
#undef INT_LEAST32_WIDTH
#define INT_LEAST32_WIDTH __INT_LEAST32_WIDTH__
#undef UINT_LEAST32_WIDTH
#define UINT_LEAST32_WIDTH __INT_LEAST32_WIDTH__
#undef INT_LEAST64_WIDTH
#define INT_LEAST64_WIDTH __INT_LEAST64_WIDTH__
#undef UINT_LEAST64_WIDTH
#define UINT_LEAST64_WIDTH __INT_LEAST64_WIDTH__
#undef INT_FAST8_WIDTH
#define INT_FAST8_WIDTH __INT_FAST8_WIDTH__
#undef UINT_FAST8_WIDTH
#define UINT_FAST8_WIDTH __INT_FAST8_WIDTH__
#undef INT_FAST16_WIDTH
#define INT_FAST16_WIDTH __INT_FAST16_WIDTH__
#undef UINT_FAST16_WIDTH
#define UINT_FAST16_WIDTH __INT_FAST16_WIDTH__
#undef INT_FAST32_WIDTH
#define INT_FAST32_WIDTH __INT_FAST32_WIDTH__
#undef UINT_FAST32_WIDTH
#define UINT_FAST32_WIDTH __INT_FAST32_WIDTH__
#undef INT_FAST64_WIDTH
#define INT_FAST64_WIDTH __INT_FAST64_WIDTH__
#undef UINT_FAST64_WIDTH
#define UINT_FAST64_WIDTH __INT_FAST64_WIDTH__
#ifdef __INTPTR_TYPE__
#undef INTPTR_WIDTH
#define INTPTR_WIDTH __INTPTR_WIDTH__
#endif
#ifdef __UINTPTR_TYPE__
#undef UINTPTR_WIDTH
#define UINTPTR_WIDTH __INTPTR_WIDTH__
#endif
#undef INTMAX_WIDTH
#define INTMAX_WIDTH __INTMAX_WIDTH__
#undef UINTMAX_WIDTH
#define UINTMAX_WIDTH __INTMAX_WIDTH__
#undef PTRDIFF_WIDTH
#define PTRDIFF_WIDTH __PTRDIFF_WIDTH__
#undef SIG_ATOMIC_WIDTH
#define SIG_ATOMIC_WIDTH __SIG_ATOMIC_WIDTH__
#undef SIZE_WIDTH
#define SIZE_WIDTH __SIZE_WIDTH__
#undef WCHAR_WIDTH
#define WCHAR_WIDTH __WCHAR_WIDTH__
#undef WINT_WIDTH
#define WINT_WIDTH __WINT_WIDTH__
-12
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@@ -1,12 +0,0 @@
/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_ARCHCTL_H
#define __ZINNIA_UAPI_ARCHCTL_H
#ifdef __x86_64__
#define __ARCHCTL_SET_FSBASE 0
#define __ARCHCTL_SET_GSBASE 1
#define __ARCHCTL_GET_FSBASE 2
#define __ARCHCTL_GET_GSBASE 3
#endif
#endif
-25
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@@ -1,25 +0,0 @@
/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_DIRENT_H
#define __ZINNIA_UAPI_DIRENT_H
#include <uapi/types.h>
#define __DT_UNKNOWN 0
#define __DT_FIFO 1
#define __DT_CHR 2
#define __DT_DIR 4
#define __DT_BLK 6
#define __DT_REG 8
#define __DT_LNK 10
#define __DT_SOCK 12
#define __DT_WHT 14
struct __dirent {
__ino_t d_ino;
__off_t d_off;
uint16_t d_reclen;
uint8_t d_type;
char d_name[256];
};
#endif
-39
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@@ -1,39 +0,0 @@
/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_EPOLL_H
#define __ZINNIA_UAPI_EPOLL_H
#include <stdint.h>
#define __EPOLLIN (1 << 0)
#define __EPOLLOUT (1 << 1)
#define __EPOLLPRI (1 << 2)
#define __EPOLLHUP (1 << 3)
#define __EPOLLERR (1 << 4)
#define __EPOLLRDHUP (1 << 5)
#define __EPOLLMSG (1 << 6)
#define __EPOLLRDNORM (1 << 7)
#define __EPOLLRDBAND (1 << 8)
#define __EPOLLWRNORM (1 << 9)
#define __EPOLLWRBAND (1 << 10)
#define __EPOLLEXCLUSIVE (1 << 11)
#define __EPOLLWAKEUP (1 << 12)
#define __EPOLLONESHOT (1 << 13)
#define __EPOLLET (1 << 14)
#define __EPOLL_CTL_ADD 1
#define __EPOLL_CTL_DEL 2
#define __EPOLL_CTL_MOD 3
union __epoll_data {
void* ptr;
int fd;
uint32_t u32;
uint64_t u64;
};
struct __epoll_event {
uint32_t events;
union __epoll_data data;
};
#endif
-140
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@@ -1,140 +0,0 @@
/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_ERRNO_H
#define __ZINNIA_UAPI_ERRNO_H
#define __EPERM 1
#define __ENOENT 2
#define __ESRCH 3
#define __EINTR 4
#define __EIO 5
#define __ENXIO 6
#define __E2BIG 7
#define __ENOEXEC 8
#define __EBADF 9
#define __ECHILD 10
#define __EAGAIN 11
#define __ENOMEM 12
#define __EACCES 13
#define __EFAULT 14
#define __ENOTBLK 15
#define __EBUSY 16
#define __EEXIST 17
#define __EXDEV 18
#define __ENODEV 19
#define __ENOTDIR 20
#define __EISDIR 21
#define __EINVAL 22
#define __ENFILE 23
#define __EMFILE 24
#define __ENOTTY 25
#define __ETXTBSY 26
#define __EFBIG 27
#define __ENOSPC 28
#define __ESPIPE 29
#define __EROFS 30
#define __EMLINK 31
#define __EPIPE 32
#define __EDOM 33
#define __ERANGE 34
#define __EDEADLK 35
#define __ENAMETOOLONG 36
#define __ENOLCK 37
#define __ENOSYS 38
#define __ENOTEMPTY 39
#define __ELOOP 40
#define __EWOULDBLOCK __EAGAIN
#define __ENOMSG 42
#define __EIDRM 43
#define __ECHRNG 44
#define __EL2NSYNC 45
#define __EL3HLT 46
#define __EL3RST 47
#define __ELNRNG 48
#define __EUNATCH 49
#define __ENOCSI 50
#define __EL2HLT 51
#define __EBADE 52
#define __EBADR 53
#define __EXFULL 54
#define __ENOANO 55
#define __EBADRQC 56
#define __EBADSLT 57
#define __EDEADLOCK __EDEADLK
#define __EBFONT 59
#define __ENOSTR 60
#define __ENODATA 61
#define __ETIME 62
#define __ENOSR 63
#define __ENONET 64
#define __ENOPKG 65
#define __EREMOTE 66
#define __ENOLINK 67
#define __EADV 68
#define __ESRMNT 69
#define __ECOMM 70
#define __EPROTO 71
#define __EMULTIHOP 72
#define __EDOTDOT 73
#define __EBADMSG 74
#define __EOVERFLOW 75
#define __ENOTUNIQ 76
#define __EBADFD 77
#define __EREMCHG 78
#define __ELIBACC 79
#define __ELIBBAD 80
#define __ELIBSCN 81
#define __ELIBMAX 82
#define __ELIBEXEC 83
#define __EILSEQ 84
#define __ERESTART 85
#define __ESTRPIPE 86
#define __EUSERS 87
#define __ENOTSOCK 88
#define __EDESTADDRREQ 89
#define __EMSGSIZE 90
#define __EPROTOTYPE 91
#define __ENOPROTOOPT 92
#define __EPROTONOSUPPORT 93
#define __ESOCKTNOSUPPORT 94
#define __EOPNOTSUPP 95
#define __ENOTSUP __EOPNOTSUPP
#define __EPFNOSUPPORT 96
#define __EAFNOSUPPORT 97
#define __EADDRINUSE 98
#define __EADDRNOTAVAIL 99
#define __ENETDOWN 100
#define __ENETUNREACH 101
#define __ENETRESET 102
#define __ECONNABORTED 103
#define __ECONNRESET 104
#define __ENOBUFS 105
#define __EISCONN 106
#define __ENOTCONN 107
#define __ESHUTDOWN 108
#define __ETOOMANYREFS 109
#define __ETIMEDOUT 110
#define __ECONNREFUSED 111
#define __EHOSTDOWN 112
#define __EHOSTUNREACH 113
#define __EALREADY 114
#define __EINPROGRESS 115
#define __ESTALE 116
#define __EUCLEAN 117
#define __ENOTNAM 118
#define __ENAVAIL 119
#define __EISNAM 120
#define __EREMOTEIO 121
#define __EDQUOT 122
#define __ENOMEDIUM 123
#define __EMEDIUMTYPE 124
#define __ECANCELED 125
#define __ENOKEY 126
#define __EKEYEXPIRED 127
#define __EKEYREVOKED 128
#define __EKEYREJECTED 129
#define __EOWNERDEAD 130
#define __ENOTRECOVERABLE 131
#define __ERFKILL 132
#define __EHWPOISON 133
#endif
-87
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@@ -1,87 +0,0 @@
/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_FCNTL_H
#define __ZINNIA_UAPI_FCNTL_H
#include <uapi/types.h>
#define __F_OK 0
#define __X_OK 1
#define __W_OK 2
#define __R_OK 4
#define __O_RDONLY (1 << 0)
#define __O_WRONLY (1 << 1)
#define __O_RDWR (__O_RDONLY | __O_WRONLY)
#define __O_CREAT (1 << 6)
#define __O_EXCL (1 << 7)
#define __O_NOCTTY (1 << 8)
#define __O_TRUNC (1 << 9)
#define __O_APPEND (1 << 10)
#define __O_NONBLOCK (1 << 11)
#define __O_DSYNC (1 << 12)
#define __O_ASYNC (1 << 13)
#define __O_DIRECT (1 << 14)
#define __O_LARGEFILE (1 << 15)
#define __O_DIRECTORY (1 << 16)
#define __O_NOFOLLOW (1 << 17)
#define __O_NOATIME (1 << 18)
#define __O_CLOEXEC (1 << 19)
#define __O_PATH (1 << 21)
#define __O_TMPFILE (1 << 22)
#define __O_SYNC (__O_DIRECTORY | __O_TMPFILE)
#define __O_RSYNC (__O_SYNC)
#define __O_EXEC (__O_PATH)
#define __O_SEARCH (__O_PATH)
#define __O_ACCMODE (__O_RDWR | __O_PATH)
#define __AT_FDCWD (-100)
#define __AT_SYMLINK_NOFOLLOW (1 << 8)
#define __AT_SYMLINK_FOLLOW (1 << 9)
#define __AT_REMOVEDIR (1 << 10)
#define __AT_EACCESS (1 << 11)
#define __AT_EMPTY_PATH (1 << 12)
#define __F_DUPFD 0
#define __F_GETFD 1
#define __F_SETFD 2
#define __F_GETFL 3
#define __F_SETFL 4
#define __F_GETLK 5
#define __F_SETLK 6
#define __F_SETLKW 7
#define __F_SETOWN 8
#define __F_GETOWN 9
#define __F_SETOWN_EX 15
#define __F_GETOWN_EX 16
#define __F_OFD_GETLK 36
#define __F_OFD_SETLK 37
#define __F_OFD_SETLKW 38
#define __F_DUPFD_CLOEXEC 1030
#define __F_RDLCK 0
#define __F_WRLCK 1
#define __F_UNLCK 2
#define __FD_CLOEXEC 1
#define __SEEK_SET 0
#define __SEEK_CUR 1
#define __SEEK_END 2
#define __POSIX_FADV_NORMAL 0
#define __POSIX_FADV_RANDOM 1
#define __POSIX_FADV_SEQUENTIAL 2
#define __POSIX_FADV_WILLNEED 3
#define __POSIX_FADV_DONTNEED 4
#define __POSIX_FADV_NOREUSE 5
struct __flock {
int16_t l_type;
int16_t l_whence;
__off_t l_start;
__off_t l_len;
__pid_t l_pid;
};
#endif
-237
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@@ -1,237 +0,0 @@
/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_INPUT_H
#define __ZINNIA_UAPI_INPUT_H
#include <stdint.h>
#include <uapi/ioctls.h>
#include <uapi/time.h>
struct __input_event {
struct __timeval time;
uint16_t type;
uint16_t code;
int32_t value;
};
struct __input_id {
uint16_t bustype;
uint16_t vendor;
uint16_t product;
uint16_t version;
};
struct __input_absinfo {
int32_t value;
int32_t minimum;
int32_t maximum;
int32_t fuzz;
int32_t flat;
int32_t resolution;
};
#define __EV_SYN 0x00
#define __EV_KEY 0x01
#define __EV_REL 0x02
#define __EV_ABS 0x03
#define __EV_MSC 0x04
#define __EV_CNT 0x20
#define __SYN_REPORT 0
#define __REL_X 0x00
#define __REL_Y 0x01
#define __REL_WHEEL 0x08
#define __REL_MAX 0x0f
#define __REL_CNT 0x10
#define __ABS_X 0x00
#define __ABS_Y 0x01
#define __ABS_Z 0x02
#define __ABS_RX 0x03
#define __ABS_RY 0x04
#define __ABS_RZ 0x05
#define __ABS_THROTTLE 0x06
#define __ABS_RUDDER 0x07
#define __ABS_WHEEL 0x08
#define __ABS_HAT0X 0x10
#define __ABS_HAT0Y 0x11
#define __ABS_MAX 0x3f
#define __ABS_CNT 0x40
#define __KEY_RESERVED 0
#define __KEY_ESC 1
#define __KEY_1 2
#define __KEY_2 3
#define __KEY_3 4
#define __KEY_4 5
#define __KEY_5 6
#define __KEY_6 7
#define __KEY_7 8
#define __KEY_8 9
#define __KEY_9 10
#define __KEY_0 11
#define __KEY_MINUS 12
#define __KEY_EQUAL 13
#define __KEY_BACKSPACE 14
#define __KEY_TAB 15
#define __KEY_Q 16
#define __KEY_W 17
#define __KEY_E 18
#define __KEY_R 19
#define __KEY_T 20
#define __KEY_Y 21
#define __KEY_U 22
#define __KEY_I 23
#define __KEY_O 24
#define __KEY_P 25
#define __KEY_LEFTBRACE 26
#define __KEY_RIGHTBRACE 27
#define __KEY_ENTER 28
#define __KEY_LEFTCTRL 29
#define __KEY_A 30
#define __KEY_S 31
#define __KEY_D 32
#define __KEY_F 33
#define __KEY_G 34
#define __KEY_H 35
#define __KEY_J 36
#define __KEY_K 37
#define __KEY_L 38
#define __KEY_SEMICOLON 39
#define __KEY_APOSTROPHE 40
#define __KEY_GRAVE 41
#define __KEY_LEFTSHIFT 42
#define __KEY_BACKSLASH 43
#define __KEY_Z 44
#define __KEY_X 45
#define __KEY_C 46
#define __KEY_V 47
#define __KEY_B 48
#define __KEY_N 49
#define __KEY_M 50
#define __KEY_COMMA 51
#define __KEY_DOT 52
#define __KEY_SLASH 53
#define __KEY_RIGHTSHIFT 54
#define __KEY_KPASTERISK 55
#define __KEY_LEFTALT 56
#define __KEY_SPACE 57
#define __KEY_CAPSLOCK 58
#define __KEY_F1 59
#define __KEY_F2 60
#define __KEY_F3 61
#define __KEY_F4 62
#define __KEY_F5 63
#define __KEY_F6 64
#define __KEY_F7 65
#define __KEY_F8 66
#define __KEY_F9 67
#define __KEY_F10 68
#define __KEY_NUMLOCK 69
#define __KEY_SCROLLLOCK 70
#define __KEY_KP7 71
#define __KEY_KP8 72
#define __KEY_KP9 73
#define __KEY_KPMINUS 74
#define __KEY_KP4 75
#define __KEY_KP5 76
#define __KEY_KP6 77
#define __KEY_KPPLUS 78
#define __KEY_KP1 79
#define __KEY_KP2 80
#define __KEY_KP3 81
#define __KEY_KP0 82
#define __KEY_KPDOT 83
#define __KEY_F11 87
#define __KEY_F12 88
#define __KEY_KPENTER 96
#define __KEY_RIGHTCTRL 97
#define __KEY_KPSLASH 98
#define __KEY_SYSRQ 99
#define __KEY_RIGHTALT 100
#define __KEY_HOME 102
#define __KEY_UP 103
#define __KEY_PAGEUP 104
#define __KEY_LEFT 105
#define __KEY_RIGHT 106
#define __KEY_END 107
#define __KEY_DOWN 108
#define __KEY_PAGEDOWN 109
#define __KEY_INSERT 110
#define __KEY_DELETE 111
#define __KEY_LEFTMETA 125
#define __KEY_RIGHTMETA 126
#define __KEY_F13 183
#define __KEY_F14 184
#define __KEY_F15 185
#define __KEY_F16 186
#define __KEY_F17 187
#define __KEY_F18 188
#define __KEY_F19 189
#define __KEY_F20 190
#define __KEY_F21 191
#define __KEY_F22 192
#define __KEY_F23 193
#define __KEY_F24 194
#define __KEY_CNT 0x300
#define __BTN_MISC 0x100
#define __BTN_LEFT 0x110
#define __BTN_RIGHT 0x111
#define __BTN_MIDDLE 0x112
#define __BTN_SIDE 0x113
#define __BTN_EXTRA 0x114
#define __BTN_FORWARD 0x115
#define __BTN_BACK 0x116
#define __BTN_TRIGGER 0x120
#define __BTN_THUMB 0x121
#define __BTN_THUMB2 0x122
#define __BTN_TOP 0x123
#define __BTN_TOP2 0x124
#define __BTN_PINKIE 0x125
#define __BTN_BASE 0x126
#define __BTN_BASE2 0x127
#define __BTN_BASE3 0x128
#define __BTN_BASE4 0x129
#define __BTN_BASE5 0x12a
#define __BTN_BASE6 0x12b
#define __BTN_SOUTH 0x130
#define __BTN_EAST 0x131
#define __BTN_C 0x132
#define __BTN_NORTH 0x133
#define __BTN_WEST 0x134
#define __BTN_Z 0x135
#define __BTN_TL 0x136
#define __BTN_TR 0x137
#define __BTN_TL2 0x138
#define __BTN_TR2 0x139
#define __BTN_SELECT 0x13a
#define __BTN_START 0x13b
#define __BTN_MODE 0x13c
#define __BTN_THUMBL 0x13d
#define __BTN_THUMBR 0x13e
#define __BUS_USB 0x03
#define __BUS_I8042 0x11
#define __EV_VERSION 0x010001
#define __EVIOCGVERSION __IOR('E', 0x01, int)
#define __EVIOCGID __IOR('E', 0x02, struct __input_id)
#define __EVIOCGNAME(len) __IOC(__IOC_OUT, 'E', 0x06, len)
#define __EVIOCGPHYS(len) __IOC(__IOC_OUT, 'E', 0x07, len)
#define __EVIOCGUNIQ(len) __IOC(__IOC_OUT, 'E', 0x08, len)
#define __EVIOCGPROP(len) __IOC(__IOC_OUT, 'E', 0x09, len)
#define __EVIOCGKEY(len) __IOC(__IOC_OUT, 'E', 0x18, len)
#define __EVIOCGLED(len) __IOC(__IOC_OUT, 'E', 0x19, len)
#define __EVIOCGSND(len) __IOC(__IOC_OUT, 'E', 0x1A, len)
#define __EVIOCGSW(len) __IOC(__IOC_OUT, 'E', 0x1B, len)
#define __EVIOCGBIT(ev, len) __IOC(__IOC_OUT, 'E', 0x20 + (ev), len)
#define __EVIOCGABS(abs) __IOR('E', 0x40 + (abs), struct __input_absinfo)
#define __EVIOCGRAB __IOW('E', 0x90, int)
#define __EVIOCREVOKE __IOW('E', 0x91, int)
#define __EVIOCSCLOCKID __IOW('E', 0xA0, int)
#endif
-51
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/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_IOCTLS_H
#define __ZINNIA_UAPI_IOCTLS_H
#define __IOC_VOID 0x00000000U
#define __IOC_OUT 0x40000000U
#define __IOC_IN 0x80000000U
#define __IOC_INOUT (__IOC_IN | __IOC_OUT)
#define __IOC(inout, group, num, len) ((inout) | (((len) & 0x3FFF) << 16) | ((group) << 8) | (num))
#define __IO(group, num) __IOC(__IOC_VOID, (group), (num), 0)
#define __IOR(group, num, type) __IOC(__IOC_OUT, (group), (num), sizeof(type))
#define __IOW(group, num, type) __IOC(__IOC_IN, (group), (num), sizeof(type))
#define __IOC_GROUP(req) (((req) >> 8) & 0xFF)
#define __IOC_NUM(req) ((req) & 0xFF)
#define __IOC_LEN(req) (((req) >> 16) & 0x3FFF)
#define __TCGETS 0x5401
#define __TCSETS 0x5402
#define __TCSETSW 0x5403
#define __TCSETSF 0x5404
#define __TCFLSH 0x540B
#define __TIOCSCTTY 0x540E
#define __TIOCGPGRP 0x540F
#define __TIOCSPGRP 0x5410
#define __TIOCGWINSZ 0x5413
#define __TIOCSWINSZ 0x5414
#define __FIONREAD 0x541B
#define __TIOCCONS 0x541D
#define __TIOCPKT 0x5420
#define __FIONBIO 0x5421
#define __TIOCNOTTY 0x5422
#define __TIOCGSID 0x5429
#define __TIOCSIG 0x5436
#define __TIOCGPKT 0x5438
#define __TIOCGNAME 0x5470
#define __TIOCGPTN __IOR('T', 0x30, int)
#define __TIOCSPTLCK __IOW('T', 0x31, int)
#define __TIOCGPTLCK 3
#define __BLKGETSIZE64 __IOR('B', 0x00, unsigned long long)
#define __BLKSSZGET __IOR('B', 0x01, unsigned int)
#define __BLKRRPART __IO('B', 0x02)
#define __TIOCPKT_DATA 0
#define __TIOCPKT_FLUSHREAD 1
#define __TIOCPKT_FLUSHWRITE 2
#define __TIOCPKT_STOP 4
#define __TIOCPKT_START 8
#endif
-10
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@@ -1,10 +0,0 @@
/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_LIMITS_H
#define __ZINNIA_UAPI_LIMITS_H
#define __PATH_MAX 4096
#define __NAME_MAX 255
#define __SYMLINK_MAX 4096
#define __PIPE_BUF 4096
#endif
-21
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@@ -1,21 +0,0 @@
/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_MMAN_H
#define __ZINNIA_UAPI_MMAN_H
#define __PROT_NONE 0x00
#define __PROT_READ 0x01
#define __PROT_WRITE 0x02
#define __PROT_EXEC 0x04
#define __MAP_FAILED ((void*)-1)
#define __MAP_FILE 0x00
#define __MAP_SHARED 0x01
#define __MAP_PRIVATE 0x02
#define __MAP_FIXED 0x10
#define __MAP_ANON 0x20
#define __MS_ASYNC 0x1
#define __MS_INVALIDATE 0x2
#define __MS_SYNC 0x4
#endif
-13
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@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_MOUNT_H
#define __ZINNIA_UAPI_MOUNT_H
#define __MNT_RDONLY (1 << 0)
#define __MNT_NOSUID (1 << 1)
#define __MNT_NOEXEC (1 << 2)
#define __MNT_RELATIME (1 << 3)
#define __MNT_NOATIME (1 << 4)
#define __MNT_REMOUNT (1 << 5)
#define __MNT_FORCE (1 << 6)
#endif
-101
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/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_NET_H
#define __ZINNIA_UAPI_NET_H
#include <stdint.h>
#include <uapi/socket.h>
#define __IFNAMSIZ 16
#define __SIOCADDRT 0x890B
#define __SIOCDELRT 0x890C
#define __SIOCGIFCONF 0x8912
#define __SIOCGIFFLAGS 0x8913
#define __SIOCSIFFLAGS 0x8914
#define __SIOCGIFADDR 0x8915
#define __SIOCSIFADDR 0x8916
#define __SIOCGIFBRDADDR 0x8919
#define __SIOCSIFBRDADDR 0x891A
#define __SIOCGIFNETMASK 0x891B
#define __SIOCSIFNETMASK 0x891C
#define __SIOCGIFMTU 0x8921
#define __SIOCSIFMTU 0x8922
#define __SIOCGIFHWADDR 0x8927
#define __SIOCGIFINDEX 0x8933
#define __IFF_UP 0x1
#define __IFF_BROADCAST 0x2
#define __IFF_LOOPBACK 0x8
#define __IFF_RUNNING 0x40
#define __IFF_MULTICAST 0x1000
#define __ARPHRD_ETHER 1
#define __RTF_UP 0x0001
#define __RTF_GATEWAY 0x0002
#define __RTF_HOST 0x0004
#define __ETH_P_ALL 0x0003
#define __ETH_P_IP 0x0800
#define __ETH_P_ARP 0x0806
#define __ETH_P_IPV6 0x86DD
#define __PACKET_HOST 0
#define __PACKET_BROADCAST 1
#define __PACKET_MULTICAST 2
#define __PACKET_OTHERHOST 3
#define __PACKET_OUTGOING 4
#define __PACKET_AUXDATA 8
struct __ifmap {
unsigned long mem_start;
unsigned long mem_end;
unsigned short base_addr;
unsigned char irq;
unsigned char dma;
unsigned char port;
};
struct __ifreq {
char ifr_name[__IFNAMSIZ];
union {
struct __sockaddr ifr_addr;
struct __sockaddr ifr_dstaddr;
struct __sockaddr ifr_broadaddr;
struct __sockaddr ifr_netmask;
struct __sockaddr ifr_hwaddr;
short ifr_flags;
int ifr_ifindex;
int ifr_mtu;
struct __ifmap ifr_map;
char ifr_slave[__IFNAMSIZ];
char ifr_newname[__IFNAMSIZ];
uintptr_t ifr_data;
};
};
struct __ifconf {
int ifc_len;
uintptr_t ifc_buf;
};
struct __rtentry {
unsigned long rt_pad1;
struct __sockaddr rt_dst;
struct __sockaddr rt_gateway;
struct __sockaddr rt_genmask;
unsigned short rt_flags;
short rt_pad2;
unsigned long rt_pad3;
unsigned char rt_tos;
unsigned char rt_class;
short rt_pad4[3];
short rt_metric;
uintptr_t rt_dev;
unsigned long rt_mtu;
unsigned long rt_window;
unsigned short rt_irtt;
};
#endif
-27
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/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_POLL_H
#define __ZINNIA_UAPI_POLL_H
#include <stdint.h>
#define __POLLIN 0x01
#define __POLLOUT 0x02
#define __POLLPRI 0x04
#define __POLLHUP 0x08
#define __POLLERR 0x10
#define __POLLRDHUP 0x20
#define __POLLNVAL 0x40
#define __POLLRDNORM 0x80
#define __POLLRDBAND 0x100
#define __POLLWRNORM 0x200
#define __POLLWRBAND 0x400
typedef intptr_t __nfds_t;
struct __pollfd {
int fd;
int16_t events;
int16_t revents;
};
#endif
-15
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@@ -1,15 +0,0 @@
/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_REBOOT_H
#define __ZINNIA_UAPI_REBOOT_H
#define __REBOOT_MAGIC 0xDEADBEEF
#define __RB_AUTOBOOT 0xdeadb007
#define __RB_HALT_SYSTEM 0xdeaddead
#define __RB_ENABLE_CAD 0xdeadcad1
#define __RB_DISABLE_CAD 0xdeadcad0
#define __RB_POWER_OFF 0xdead00ff
#define __RB_SW_SUSPEND 0xdead2222
#define __RB_KEXEC 0xdeadecec
#endif
-54
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/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_RESOURCE_H
#define __ZINNIA_UAPI_RESOURCE_H
#include <uapi/time.h>
#include <uapi/types.h>
#define __PRIO_PROCESS 0
#define __PRIO_PGRP 1
#define __PRIO_USER 2
#define __RLIMIT_CPU 0
#define __RLIMIT_FSIZE 1
#define __RLIMIT_DATA 2
#define __RLIMIT_STACK 3
#define __RLIMIT_CORE 4
#define __RLIMIT_RSS 5
#define __RLIMIT_NPROC 6
#define __RLIMIT_NOFILE 7
#define __RLIMIT_MEMLOCK 8
#define __RLIMIT_AS 9
#define __RLIMIT_NLIMITS 16
#define __RUSAGE_SELF 0
#define __RUSAGE_CHILDREN (-1)
#define __RUSAGE_THREAD 1
#define __RLIM_INFINITY ((__rlim_t) - 1)
struct __rlimit {
__rlim_t rlim_cur;
__rlim_t rlim_max;
};
struct __rusage {
struct __timeval ru_utime;
struct __timeval ru_stime;
long ru_maxrss;
long ru_ixrss;
long ru_idrss;
long ru_isrss;
long ru_minflt;
long ru_majflt;
long ru_nswap;
long ru_inblock;
long ru_oublock;
long ru_msgsnd;
long ru_msgrcv;
long ru_nsignals;
long ru_nvcsw;
long ru_nivcsw;
};
#endif
-156
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/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_SIGNAL_H
#define __ZINNIA_UAPI_SIGNAL_H
#include <stddef.h>
#include <uapi/types.h>
#define __SIGABRT 1
#define __SIGALRM 2
#define __SIGBUS 3
#define __SIGCHLD 4
#define __SIGCONT 5
#define __SIGFPE 6
#define __SIGHUP 7
#define __SIGILL 8
#define __SIGINT 9
#define __SIGKILL 10
#define __SIGPIPE 11
#define __SIGQUIT 12
#define __SIGSEGV 13
#define __SIGSTOP 14
#define __SIGTERM 15
#define __SIGTSTP 16
#define __SIGTTIN 17
#define __SIGTTOU 18
#define __SIGUSR1 19
#define __SIGUSR2 20
#define __SIGWINCH 21
#define __SIGSYS 22
#define __SIGTRAP 23
#define __SIGURG 24
#define __SIGVTALRM 25
#define __SIGXCPU 26
#define __SIGXFSZ 27
#define __SIGIO 28
#define __SIGPOLL 29
#define __SIGPROF 30
#define __SIGPWR 31
#define __SIGIOT 32
#define __SIGCANCEL 33
#define __SIGRTMIN 35
#define __SIGRTMAX 64
#define __NSIG 65
#define __SIG_DFL 0
#define __SIG_IGN 1
#define __SIG_BLOCK 1
#define __SIG_UNBLOCK 2
#define __SIG_SETMASK 3
#define __SA_NOCLDSTOP (1 << 0)
#define __SA_ONSTACK (1 << 1)
#define __SA_RESETHAND (1 << 2)
#define __SA_RESTART (1 << 3)
#define __SA_SIGINFO (1 << 4)
#define __SA_NOCLDWAIT (1 << 5)
#define __SA_NODEFER (1 << 6)
#define __MINSIGSTKSZ 2048
#define __SS_ONSTACK 1
#define __SS_DISABLE 2
#define __SIGEV_NONE 1
#define __SIGEV_SIGNAL 2
#define __SIGEV_THREAD 3
#define __SI_TKILL (-6)
#define __SI_TIMER (-2)
#define __SI_QUEUE (-1)
#define __SI_USER 0
#define __SI_KERNEL 128
#define __ILL_ILLOPC 1
#define __FPE_INTDIV 1
#define __SEGV_MAPERR 1
#define __SEGV_ACCERR 2
#define __BUS_ADRALN 1
#define __TRAP_BRKPT 1
#define __CLD_EXITED 1
#define __CLD_KILLED 2
#define __CLD_DUMPED 3
#define __CLD_TRAPPED 4
#define __CLD_STOPPED 5
#define __CLD_CONTINUED 6
typedef uint64_t __sigset_t;
union __sigval {
int sival_int;
void* sival_ptr;
};
struct __siginfo {
int si_signo;
int si_code;
int si_errno;
__pid_t si_pid;
__uid_t si_uid;
void* si_addr;
int si_status;
union __sigval si_value;
};
struct __sigaction {
uintptr_t sa_handler;
unsigned long sa_flags;
uintptr_t sa_restorer;
__sigset_t sa_mask;
};
struct __stack {
void* ss_sp;
size_t ss_size;
int ss_flags;
};
struct __sigevent {
union __sigval sigev_value;
int sigev_notify;
int sigev_signo;
void (*sigev_notify_function)(union __sigval);
void* sigev_notify_attributes;
__pid_t sigev_notify_thread_id;
};
#define __SFD_CLOEXEC __O_CLOEXEC
#define __SFD_NONBLOCK __O_NONBLOCK
struct __signalfd_siginfo {
uint32_t ssi_signo;
int32_t ssi_errno;
int32_t ssi_code;
uint32_t ssi_pid;
uint32_t ssi_uid;
int32_t ssi_fd;
uint32_t ssi_tid;
uint32_t ssi_band;
uint32_t ssi_overrun;
uint32_t ssi_trapno;
int32_t ssi_status;
int32_t ssi_int;
uint64_t ssi_ptr;
uint64_t ssi_utime;
uint64_t ssi_stime;
uint64_t ssi_addr;
uint16_t ssi_addr_lsb;
uint16_t __pad2;
int32_t ssi_syscall;
uint64_t ssi_call_addr;
uint32_t ssi_arch;
uint8_t __pad[28];
};
#endif
-159
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/* SPDX-License-Identifier: Unlicense */
#ifndef __ZINNIA_UAPI_SOCKET_H
#define __ZINNIA_UAPI_SOCKET_H
#include <stdint.h>
#include <uapi/types.h>
typedef uint32_t __socklen_t;
typedef uint16_t __sa_family_t;
struct __msghdr {
uintptr_t msg_name;
__socklen_t msg_namelen;
uintptr_t msg_iov;
int msg_iovlen;
uintptr_t msg_control;
__socklen_t msg_controllen;
int msg_flags;
};
struct __cmsghdr {
__socklen_t cmsg_len;
int cmsg_level;
int cmsg_type;
};
struct __sockaddr {
__sa_family_t sa_family;
char sa_data[14];
};
struct __sockaddr_storage {
__sa_family_t ss_family;
char __padding[128 - sizeof(__sa_family_t) - sizeof(uintptr_t)];
uintptr_t __alignment;
};
struct __sockaddr_un {
__sa_family_t sun_family;
char sun_path[108];
};
typedef uint32_t __in_addr_t;
typedef uint16_t __in_port_t;
struct __in_addr {
__in_addr_t s_addr;
};
struct __sockaddr_in {
__sa_family_t sin_family;
__in_port_t sin_port;
struct __in_addr sin_addr;
uint8_t sin_zero[8];
};
struct __in6_addr {
uint8_t s6_addr[16];
};
struct __sockaddr_in6 {
__sa_family_t sin6_family;
__in_port_t sin6_port;
uint32_t sin6_flowinfo;
struct __in6_addr sin6_addr;
uint32_t sin6_scope_id;
};
struct __sockaddr_ll {
__sa_family_t sll_family;
uint16_t sll_protocol;
int32_t sll_ifindex;
uint16_t sll_hatype;
uint8_t sll_pkttype;
uint8_t sll_halen;
uint8_t sll_addr[8];
};
struct __ucred {
__pid_t pid;
__uid_t uid;
__gid_t gid;
};
#define __SCM_RIGHTS 1
#define __SCM_CREDENTIALS 0x02
#define __SOCK_DGRAM (1 << 0)
#define __SOCK_RAW (1 << 1)
#define __SOCK_STREAM (1 << 2)
#define __SOCK_SEQPACKET (1 << 3)
#define __SOCK_NONBLOCK (1 << 15)
#define __SOCK_CLOEXEC (1 << 16)
#define __SOCK_CLOFORK (1 << 17)
#define __SOL_IP 0
#define __SOL_SOCKET 1
#define __SOL_PACKET 263
#define __SO_ACCEPTCONN 1
#define __SO_BROADCAST 2
#define __SO_DEBUG 3
#define __SO_DONTROUTE 4
#define __SO_ERROR 5
#define __SO_KEEPALIVE 6
#define __SO_LINGER 7
#define __SO_OOBINLINE 8
#define __SO_RCVBUF 9
#define __SO_RCVLOWAT 10
#define __SO_RCVTIMEO 11
#define __SO_REUSEADDR 12
#define __SO_SNDBUF 13
#define __SO_SNDLOWAT 14
#define __SO_SNDTIMEO 15
#define __SO_TYPE 16
#define __SO_SNDBUFFORCE 17
#define __SO_PEERCRED 18
#define __SO_ATTACH_FILTER 19
#define __SO_PASSCRED 20
#define __SO_RCVBUFFORCE 21
#define __SO_DETACH_FILTER 22
#define __SO_PROTOCOL 23
#define __SO_REUSEPORT 24
#define __SO_BINDTODEVICE 27
#define __SO_DOMAIN 28
#define __SOMAXCONN 128
#define __MSG_CTRUNC 0x1
#define __MSG_DONTROUTE 0x2
#define __MSG_EOR 0x4
#define __MSG_OOB 0x8
#define __MSG_NOSIGNAL 0x10
#define __MSG_PEEK 0x20
#define __MSG_TRUNC 0x40
#define __MSG_WAITALL 0x80
#define __MSG_FIN 0x200
#define __MSG_CONFIRM 0x800
#define __MSG_DONTWAIT 0x1000
#define __MSG_CMSG_CLOEXEC 0x2000
#define __MSG_MORE 0x4000
#define __AF_UNSPEC 0
#define __AF_INET 1
#define __AF_INET6 2
#define __AF_UNIX 3
#define __AF_PACKET 11
#define __IPPROTO_IP 0
#define __IPPROTO_ICMP 1
#define __IPPROTO_TCP 6
#define __IPPROTO_UDP 17
#define __IPPROTO_RAW 255
#define __SHUT_RD 1
#define __SHUT_WR 2
#define __SHUT_RDWR (__SHUT_RD | __SHUT_WR)
#endif

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