Rename dirs

.clangd

@@ -1,2 +1,2 @@
 Style:
-  AngledHeaders: [ "zinnia/.*", " kernel/.*" ]
+  AngledHeaders: [ "zinnia/.*", "uapi/.*" ]

.gitignore

@@ -0,0 +1,8 @@
+.config*
+build/
+.cache/
+.wraplock
+*.o
+*.a
+*.so
+__pycache__/

Kconfig

@@ -0,0 +1,10 @@
+mainmenu "Zinnia Kernel Configuration"
+
+config KERNEL_FLAVOR
+  string "Kernel flavor name"
+  default "vanilla"
+
+source "arch/$(ARCH)/Kconfig"
+source "mem/Kconfig"
+source "sched/Kconfig"
+source "dev/Kconfig"

LICENSE

@@ -1,21 +0,0 @@
-MIT License
-
-Copyright (c) 2026 Marvin Friedrich
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.

LICENSE

@@ -0,0 +1 @@
+LICENSES/ISC.txt

LICENSES/ISC.txt

@@ -0,0 +1,7 @@
+ISC License
+
+Copyright 2026 Marvin Friedrich and contributors
+
+Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

LICENSES/Unlicense.txt

@@ -0,0 +1,10 @@
+This is free and unencumbered software released into the public domain.
+
+Anyone is free to copy, modify, publish, use, compile, sell, or distribute this software, either in source code form or as a compiled binary, for any purpose, commercial or non-commercial, and by any means.
+
+In jurisdictions that recognize copyright laws, the author or authors of this software dedicate any and all copyright interest in the software to the public domain. We make this dedication for the benefit of the public at large and to the detriment of our heirs and
+successors. We intend this dedication to be an overt act of relinquishment in perpetuity of all present and future rights to this software under copyright law.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+For more information, please refer to <http://unlicense.org/>

README.md

@@ -1,20 +1,27 @@
+<img src="logo.svg" width="10%"/>
+
 # Zinnia
 
-![GitHub License](https://img.shields.io/github/license/zinnia-os/zinnia?style=flat&color=blue)
+![GitHub License](https://img.shields.io/github/license/zinnia-os/zinnia?style=flat&color=green)
+![GitHub top language](https://img.shields.io/github/languages/top/zinnia-os/zinnia)
 ![GitHub Repo stars](https://img.shields.io/github/stars/zinnia-os/zinnia?style=flat)
+![GitHub Actions Workflow Status](https://img.shields.io/github/actions/workflow/status/zinnia-os/zinnia/ci.yml)
 ![GitHub Issues or Pull Requests](https://img.shields.io/github/issues/zinnia-os/zinnia?style=flat)
+![Discord](https://img.shields.io/discord/1305893510704267327?logo=discord&logoColor=white&label=discord)
 
-Zinnia is a lightweight Unix-like microkernel targeting 64-bit devices.
+Zinnia is a lightweight Unix-like monolithic kernel targeting 64-bit devices.
 
 ## Building Zinnia
 
-To build the kernel and the servers you need `meson` and a C23-compatible
-GNU-like compiler targeting Zinnia.
-Currently supported are GCC and Clang toolchains.
+To build the kernel you need:
+- `meson`
+- a `kconfig` frontend (like `kconfiglib` via `pip`)
+- a GNU-like C compiler with support for C23 (e.g. `gcc` or `clang`)
 
 To configure, run:
 ```sh
-meson setup -Dbuild_kernel=true -Dbuild_servers=true $build_dir
+alldefconfig
+meson setup $build_dir
 ```
 
 And to build:

arch/x86_64/Kconfig

@@ -0,0 +1,17 @@
+menu "x86_64 Architecture options"
+
+config X86_64
+  bool
+  default y
+  select ACPI
+  select HAVE_MMU
+  select HAVE_MMU_GENERIC
+  select HAVE_TLB_SHOOTDOWN_IPI
+  help
+    64-bit x86 CPU support for AMD and Intel CPUs.
+
+config TSC
+  bool "Invariant Timestamp Counter support"
+  default y
+
+endmenu

arch/x86_64/acpi.c

@@ -0,0 +1,36 @@
+#include <stdckdint.h>
+#include <stdint.h>
+#include <uacpi/kernel_api.h>
+#include <uacpi/status.h>
+#include <x86_64/asm.h>
+
+uacpi_status uacpi_kernel_io_map(uacpi_io_addr base, uacpi_size len, uacpi_handle* out_handle) {
+    uintptr_t end;
+    if (ckd_add(&end, base, len) || end > 0x10000)
+        return UACPI_STATUS_INVALID_ARGUMENT;
+    *out_handle = (uacpi_handle)(uintptr_t)base;
+    return UACPI_STATUS_OK;
+}
+
+void uacpi_kernel_io_unmap(uacpi_handle handle) {
+    // Left intentionally blank.
+}
+
+#define IO_READ(width, suffix) \
+    uacpi_status uacpi_kernel_io_read##width(uacpi_handle handle, uacpi_size offset, uacpi_u##width* out_value) { \
+        *out_value = asm_in##suffix((uintptr_t)handle + offset); \
+        return UACPI_STATUS_OK; \
+    }
+
+#define IO_WRITE(width, suffix) \
+    uacpi_status uacpi_kernel_io_write##width(uacpi_handle handle, uacpi_size offset, uacpi_u##width in_value) { \
+        asm_out##suffix((uintptr_t)handle + offset, in_value); \
+        return UACPI_STATUS_OK; \
+    }
+
+IO_READ(8, b)
+IO_READ(16, w)
+IO_READ(32, l)
+IO_WRITE(8, b)
+IO_WRITE(16, w)
+IO_WRITE(32, l)

arch/x86_64/apic.c

@@ -0,0 +1,163 @@
+#include <zinnia/alloc.h>
+#include <zinnia/assert.h>
+#include <zinnia/clock.h>
+#include <zinnia/mmio.h>
+#include <zinnia/percpu.h>
+#include <zinnia/pmap.h>
+#include <zinnia/utils.h>
+#include <zinnia/vma.h>
+#include <arch/cpu.h>
+#include <arch/timer.h>
+#include <stdint.h>
+#include <x86_64/apic.h>
+#include <x86_64/asm.h>
+#include <x86_64/defs.h>
+#include <x86_64/percpu.h>
+
+static uint32_t lapic_msr(size_t offset) {
+    return 0x800 + (offset >> 4);
+}
+
+static uint32_t lapic_read_reg(struct local_apic* lapic, mmio_reg32 reg) {
+    if (lapic->xapic_regs)
+        return mmio_reg_read(lapic->xapic_regs, reg);
+    else
+        return asm_rdmsr(lapic_msr(reg.offset));
+}
+
+static void lapic_write_reg(struct local_apic* lapic, mmio_reg32 reg, uint32_t value) {
+    if (lapic->xapic_regs)
+        mmio_reg_write(lapic->xapic_regs, reg, value);
+    else
+        asm_wrmsr(lapic_msr(reg.offset), value);
+}
+
+static uint64_t lapic_read_icr(struct local_apic* lapic) {
+    if (lapic->xapic_regs) {
+        uint64_t lo = mmio_reg_read(lapic->xapic_regs, APIC_REG_ICR_LO);
+        uint64_t hi = mmio_reg_read(lapic->xapic_regs, APIC_REG_ICR_HI);
+        return (hi << 32) | lo;
+    } else {
+        return asm_rdmsr(lapic_msr(APIC_REG_ICR.offset));
+    }
+}
+
+static void lapic_write_icr(struct local_apic* lapic, uint64_t value) {
+    if (lapic->xapic_regs) {
+        mmio_reg_write(lapic->xapic_regs, APIC_REG_ICR_HI, (uint32_t)(value >> 32));
+        mmio_reg_write(lapic->xapic_regs, APIC_REG_ICR_LO, (uint32_t)value);
+    } else {
+        asm_wrmsr(lapic_msr(APIC_REG_ICR.offset), value);
+    }
+}
+
+void lapic_init(struct local_apic* lapic) {
+    uint64_t apic_msr = asm_rdmsr(0x1B);
+    apic_msr |= 1 << 11; // Enable APIC.
+
+    struct cpuid cpuid = asm_cpuid(1, 0);
+    if (cpuid.ecx & CPUID_1C_X2APIC)
+        apic_msr |= 1 << 10;
+    else {
+        uintptr_t vaddr = vm_alloc(0x1000);
+        pmap_map(&kernel_vma.pmap, vaddr, apic_msr & 0xFFFF'F000, PTE_READ | PTE_WRITE, CACHE_MMIO);
+        lapic->xapic_regs = (void*)vaddr;
+        assert(lapic->xapic_regs, "Failed to allocate virtual memory!");
+    }
+
+    asm_wrmsr(0x1B, apic_msr);
+
+    lapic->id = lapic_read_reg(lapic, APIC_REG_ID);
+    if (lapic->xapic_regs)
+        lapic->id = mmio_field_get(APIC_ID_XAPIC, lapic->id);
+
+    // Reset the TPR.
+    lapic_write_reg(lapic, APIC_REG_TPR, 0);
+    // Enable APIC bit in the SIVR.
+    uint32_t sivr = lapic_read_reg(lapic, APIC_REG_SIVR);
+    sivr |= mmio_field(APIC_SIVR_VECTOR, IDT_SPURIOUS);
+    sivr |= mmio_field(APIC_SIVR_ENABLE, 1);
+    lapic_write_reg(lapic, APIC_REG_SIVR, sivr);
+
+    if (lapic->xapic_regs) {
+        lapic_write_reg(lapic, APIC_REG_DFR, 0xF000'0000);
+        // Logical destination = LAPIC ID.
+        lapic_write_reg(lapic, APIC_REG_LDR, lapic_read_reg(lapic, APIC_REG_ID));
+    }
+
+    // TODO: Parse MADT and setup NMI sources.
+
+    // Tell the APIC timer to divide by 16.
+    lapic_write_reg(lapic, APIC_REG_DCR, 3);
+    // Set the timer to the highest value possible.
+    lapic_write_reg(lapic, APIC_REG_ICR_TIMER, 0xFFFF'FFFF);
+
+    // Sleep for 10 milliseconds.
+    clock_spin_ns(10'000'000);
+
+    lapic->ticks_per_10ms = 0xFFFF'FFFF - lapic_read_reg(lapic, APIC_REG_CCR);
+    lapic_write_reg(lapic, APIC_REG_LVT_TR, mmio_field(APIC_LVT_TR_VECTOR, IDT_TIMER));
+    lapic_write_reg(lapic, APIC_REG_ICR_TIMER, 0);
+}
+
+void arch_timer_program(uint64_t deadline_ns) {
+    struct local_apic* lapic = &percpu_ref(arch_data)->lapic;
+    const uint64_t now = clock_get_elapsed_ns();
+    const uint64_t delta = MIN(deadline_ns > now ? deadline_ns - now : 0, 1'000'000'000);
+    const uint64_t ticks = delta * lapic->ticks_per_10ms / 10'000'000;
+    lapic_write_reg(lapic, APIC_REG_ICR_TIMER, MIN(MAX(ticks, 1), 0xFFFF'FFFF));
+}
+
+void lapic_eoi(struct local_apic* lapic) {
+    lapic_write_reg(lapic, APIC_REG_EOI, 0);
+}
+
+void lapic_send_ipi(
+    struct local_apic* lapic,
+    uint32_t target,
+    uint8_t vector,
+    enum apic_delivery_mode delivery_mode,
+    enum apic_dest_mode dest_mode,
+    enum apic_level level,
+    enum apic_trigger_mode trigger_mode
+) {
+    uint64_t icr = mmio_field(APIC_ICR_VECTOR, vector);
+    icr |= mmio_field(APIC_ICR_DELIVERY_MODE, delivery_mode);
+    icr |= mmio_field(APIC_ICR_DEST_MODE, dest_mode);
+    icr |= mmio_field(APIC_ICR_LEVEL, level);
+    icr |= mmio_field(APIC_ICR_TRIGGER_MODE, trigger_mode);
+
+    if (lapic->xapic_regs)
+        icr |= mmio_field(APIC_ICR_DEST_XAPIC, target);
+    else
+        icr |= mmio_field(APIC_ICR_DEST_X2APIC, target);
+
+    lapic_write_icr(lapic, icr);
+
+    if (lapic->xapic_regs) {
+        while (mmio_field_get(APIC_ICR_DELIVERY_STATUS, lapic_read_icr(lapic)) == APIC_DELIVERY_STATUS_PENDING)
+            arch_cpu_pause();
+    }
+}
+
+constexpr uint16_t PIC1_COMMAND_PORT = 0x20;
+constexpr uint16_t PIC1_DATA_PORT = 0x21;
+constexpr uint16_t PIC2_COMMAND_PORT = 0xA0;
+constexpr uint16_t PIC2_DATA_PORT = 0xA1;
+
+void pic_disable() {
+    // We initialize the PIC properly, but completely disable it and use the APIC in favor of it.
+    // Remap IRQs so they start at 0x20 since interrupts 0x00..0x1F are used by CPU exceptions.
+    asm_outb(PIC1_COMMAND_PORT, 0x11);
+    asm_outb(PIC1_DATA_PORT, 0x20);
+    asm_outb(PIC1_DATA_PORT, 0x04);
+    asm_outb(PIC1_DATA_PORT, 0x01);
+    asm_outb(PIC1_DATA_PORT, 0xFF);
+
+    // Same for the slave PIC.
+    asm_outb(PIC2_COMMAND_PORT, 0x11);
+    asm_outb(PIC2_DATA_PORT, 0x28);
+    asm_outb(PIC2_DATA_PORT, 0x02);
+    asm_outb(PIC2_DATA_PORT, 0x01);
+    asm_outb(PIC2_DATA_PORT, 0xFF);
+}

arch/x86_64/archctl.c

@@ -0,0 +1,32 @@
+#include <zinnia/errno.h>
+#include <zinnia/syscall.h>
+#include <arch/archctl.h>
+#include <arch/mem.h>
+#include <uapi/archctl.h>
+#include <x86_64/asm.h>
+#include <x86_64/defs.h>
+
+struct syscall_ret arch_archctl(uintptr_t op, uintptr_t arg) {
+    struct syscall_ret ret = {};
+
+    switch (op) {
+    case __ARCHCTL_SET_FSBASE:
+        if (!arch_mem_addr_is_user(arg)) {
+            ret.error = EINVAL;
+            return ret;
+        }
+        asm_wrmsr(MSR_FS_BASE, arg);
+        return ret;
+    case __ARCHCTL_SET_GSBASE:
+        if (!arch_mem_addr_is_user(arg)) {
+            ret.error = EINVAL;
+            return ret;
+        }
+        // Update the inactive GSBASE MSR, not ours.
+        asm_wrmsr(MSR_KERNEL_GS_BASE, arg);
+        return ret;
+    default:
+        ret.error = EINVAL;
+        return ret;
+    }
+}

arch/x86_64/gdt.c

@@ -1,14 +1,14 @@
-#include <kernel/percpu.h>
-#include <kernel/syscalls.h>
+#include <zinnia/percpu.h>
 #include <stddef.h>
 #include <string.h>
 #include <x86_64/asm.h>
 #include <x86_64/defs.h>
 #include <x86_64/gdt.h>
+#include <x86_64/percpu.h>
 #include <x86_64/tss.h>
 
-static const struct gdt main_gdt = {
-    .null = {.val = 0},
+const struct gdt gdt_base = {
+    .null = {0},
     .kernel_code32 = {.val = 0x00cf9b000000ffff},
     .kernel_data32 = {.val = 0x00cf93000000ffff},
     .kernel_code64 = {.val = 0x00a09b0000000000},
@@ -18,17 +18,17 @@ static const struct gdt main_gdt = {
     .user_code64 = {.val = 0x00a0fb0000000000},
     .tss = {
         .limit0 = sizeof(struct tss) - 1,
-        .access = 0x89, // Present | DPL = 0 | System | 64-bit TSS
+        .access = 0x89, // Present | DPL=0 | System | 64-bit TSS
         .limit1_flags = ((sizeof(struct tss) - 1) >> 16) & 0x0F,
         .reserved = 0,
     },
 };
 
 void gdt_load() {
-    struct gdt* gdt = &percpu_get()->arch.gdt;
-    memcpy(gdt, &main_gdt, sizeof(main_gdt));
+    struct gdt* gdt = &percpu_ref(arch_data)->gdt;
+    memcpy(gdt, &gdt_base, sizeof(gdt_base));
 
-    struct tss* tss = &percpu_get()->arch.tss;
+    struct tss* tss = &percpu_ref(arch_data)->tss;
     tss->iopb = sizeof(struct tss);
 
     uintptr_t tss_addr = (uintptr_t)tss;

arch/x86_64/hpet.c

@@ -0,0 +1,85 @@
+#include <zinnia/acpi.h>
+#include <zinnia/assert.h>
+#include <zinnia/clock.h>
+#include <zinnia/cmdline.h>
+#include <zinnia/initgraph.h>
+#include <zinnia/mmio.h>
+#include <zinnia/percpu.h>
+#include <zinnia/pmap.h>
+#include <zinnia/print.h>
+#include <zinnia/utils.h>
+#include <zinnia/vma.h>
+#include <uacpi/acpi.h>
+#include <uacpi/status.h>
+#include <uacpi/tables.h>
+#include <uacpi/uacpi.h>
+
+static bool use_hpet = true;
+static void hpet_option(bool use) {
+    use_hpet = use;
+}
+CMDLINE_OPTION("x86_64.hpet", "Enable High Precision Event Timer clock", hpet_option);
+
+struct hpet {
+    struct clock clock;
+    void* regs;
+    uint32_t period;
+};
+
+constexpr mmio_reg64 HPET_REG_CAP = {.offset = 0x0};
+constexpr mmio_field64 HPET_CAP_PERIOD = {HPET_REG_CAP, 32, 32};
+constexpr mmio_reg64 HPET_REG_CFG = {.offset = 0x10};
+constexpr mmio_field64 HPET_CFG_ENABLE = {HPET_REG_CFG, 0, 1};
+constexpr mmio_reg64 HPET_REG_COUNTER = {.offset = 0xF0};
+
+static void hpet_reset(struct clock* c) {
+    struct hpet* hpet = containerof(c, struct hpet, clock);
+    mmio_reg_write(hpet->regs, HPET_REG_COUNTER, 0);
+}
+
+static uint64_t hpet_get_elapsed_ns(struct clock* c) {
+    struct hpet* hpet = containerof(c, struct hpet, clock);
+    uint64_t counter = mmio_reg_read(hpet->regs, HPET_REG_COUNTER);
+    return (uint64_t)((__uint128_t)counter * (__uint128_t)hpet->period / 1'000'000);
+}
+
+static struct hpet hpet_clock = {
+    .clock = {
+        .name = "hpet",
+        .priority = 128,
+        .reset = hpet_reset,
+        .get_elapsed_ns = hpet_get_elapsed_ns,
+    },
+};
+
+static void hpet_init(struct boot_info*) {
+    if (!use_hpet)
+        return;
+
+    uacpi_table table = {0};
+    if (uacpi_table_find_by_signature("HPET", &table) != UACPI_STATUS_OK) {
+        log("x86_64/hpet: No HPET table found\n");
+        return;
+    }
+
+    struct acpi_hpet* hpet = table.ptr;
+
+    uintptr_t vaddr = vm_alloc(0x1000);
+    pmap_map(&kernel_vma.pmap, vaddr, hpet->address.address, PTE_READ | PTE_WRITE, CACHE_MMIO);
+    hpet_clock.regs = (void*)vaddr;
+
+    uacpi_table_unref(&table);
+    log("x86_64/hpet: HPET registers mapped at %p\n", hpet_clock.regs);
+
+    uint64_t cfg = mmio_reg_read(hpet_clock.regs, HPET_REG_CFG);
+    cfg |= mmio_field(HPET_CFG_ENABLE, 1);
+    mmio_reg_write(hpet_clock.regs, HPET_REG_CFG, cfg);
+
+    uint64_t cap = mmio_reg_read(hpet_clock.regs, HPET_REG_CAP);
+    hpet_clock.period = mmio_field_get(HPET_CAP_PERIOD, cap);
+
+    assert(clock_switch(&hpet_clock.clock), "Unable to switch to HPET!");
+}
+INIT_TASK(hpet_stage, "arch.x86_64.hpet", hpet_init);
+INIT_DEPENDS(hpet_stage, acpi_stage);
+INIT_ENTAILS(hpet_stage, percpu_stage);

arch/x86_64/idt.c

@@ -1,16 +1,22 @@
-#include <common/compiler.h>
-#include <kernel/irq.h>
-#include <kernel/panic.h>
-#include <kernel/percpu.h>
-#include <kernel/print.h>
-#include <kernel/sched.h>
-#include <assert.h>
+#include <zinnia/assert.h>
+#include <zinnia/compiler.h>
+#include <zinnia/irq.h>
+#include <zinnia/panic.h>
+#include <zinnia/percpu.h>
+#include <zinnia/pmap.h>
+#include <zinnia/print.h>
+#include <zinnia/sched.h>
+#include <zinnia/usercopy.h>
+#include <zinnia/utils.h>
+#include <zinnia/vma.h>
+#include <arch/sched.h>
 #include <bits/sched.h>
 #include <stddef.h>
 #include <stdint.h>
 #include <x86_64/apic.h>
 #include <x86_64/defs.h>
 #include <x86_64/gdt.h>
+#include <x86_64/percpu.h>
 
 struct [[__packed]] idt_entry {
     uint16_t base0;
@@ -33,31 +39,73 @@ static_assert(sizeof(struct idtr) == 10);
 
 void interrupt_handler(struct arch_context* ctx) {
     struct percpu* cpu = percpu_get();
-    bool old = irq_set_interrupted(true);
-
+    struct arch_percpu* arch_cpu = percpu_ref(arch_data);
     uint64_t isr = ctx->isr;
+
     switch (isr) {
     case IDT_PF:
         uint64_t cr2;
         asm volatile("mov %0, cr2" : "=r"(cr2));
-        panic("Page fault at %#lx, accessed: %#lx\n", ctx->rip, cr2);
-    case IDT_IPI_RESCHED:
-        arch_sched_preempt_disable();
-        if (arch_sched_preempt_enable()) {
-            lapic_eoi(&cpu->arch.lapic);
-            sched_reschedule(&cpu->sched);
+
+        const struct vma_fault_info info = {
+            .ip = ctx->rip,
+            .addr = cr2,
+            .caused_by_user = (ctx->cs & CPL_USER) == CPL_USER,
+            .caused_by_write = ctx->error & (1 << 1),
+            .caused_by_fetch = ctx->error & (1 << 4),
+            .page_was_present = ctx->error & (1 << 0),
+        };
+
+        struct task* current = cpu->sched.current;
+        const bool irqs_were_on = ctx->rflags & RFLAGS_IF;
+        if (irqs_were_on)
+            irq_set_state(true);
+
+        const bool handled = current && current->space && vma_page_fault(current->space, &info);
+
+        if (irqs_were_on)
+            irq_set_state(false);
+
+        if (handled)
+            break;
+
+        if (current && current->usercopy_region) {
+            struct usercopy_region* region = current->usercopy_region;
+            if (ctx->rip >= (uintptr_t)region->start_ip && ctx->rip < (uintptr_t)region->end_ip) {
+                ctx->rip = (uintptr_t)region->fault_ip;
+                break;
+            }
         }
+
+        panic(
+            "Unrecoverable page fault. Attempted to %s a %s page at %#lx (IP: %#lx)\n",
+            info.caused_by_write       ? "write to"
+                : info.caused_by_fetch ? "execute on"
+                                       : "read from",
+            info.page_was_present ? "present" : "non-present",
+            info.addr,
+            info.ip
+        );
+    case IDT_SPURIOUS:
         break;
-    case 0x20 ...(0x20 + ARRAY_SIZE(cpu->arch.irq_lines)):
-        struct irq_line* line = cpu->arch.irq_lines[isr - 0x20];
-        assert(line, "Unhandled interrupt on ISR %lu\n", isr);
-        // TODO: irq_raise(line);
+    case IDT_IPI_RESCHED:
+        lapic_eoi(&arch_cpu->lapic);
+        arch_sched_preempt_disable();
+        if (arch_sched_preempt_enable())
+            sched_reschedule(&cpu->sched);
+        break;
+    case IDT_IPI_SHOOTDOWN:
+        lapic_eoi(&arch_cpu->lapic);
+        pmap_shootdown_handle();
         break;
     default:
-        panic("Unhandled exception on ISR %lu\n", isr);
+        if (isr < 0x20)
+            panic("Unhandled exception %lu at %#lx, error: %#lx\n", isr, ctx->rip, ctx->error);
+        assert(isr - 0x20 < ARRAY_SIZE(arch_cpu->irq_lines), "Unhandled interrupt on ISR %lu", isr);
+        struct irq_line* line = arch_cpu->irq_lines[isr - 0x20];
+        assert(line, "Unhandled interrupt on ISR %lu", isr);
+        irq_line_raise(line);
     }
-
-    irq_set_interrupted(old);
 }
 
 #define CS_OFFSET (sizeof(struct arch_context) - sizeof(uint64_t) - offsetof(struct arch_context, cs))
@@ -197,6 +245,7 @@ static struct idt_entry idt[256] = {};
 
 void idt_init() {
     REPEAT_256(INTERRUPT_SETUP)
+    idt[IDT_BP].attrib |= CPL_USER << 5;
 }
 
 void idt_load() {

arch/x86_64/include/bits/cpu.h

@@ -0,0 +1,5 @@
+#pragma once
+
+static inline void arch_cpu_pause() {
+    asm volatile("pause");
+}

arch/x86_64/include/bits/elf.h

@@ -0,0 +1,34 @@
+#pragma once
+
+#include <zinnia/elf.h>
+
+#define ELF_ARCH_CLASS   ELFCLASS64
+#define ELF_ARCH_DATA    ELFDATA2LSB
+#define ELF_ARCH_MACHINE EM_X86_64
+
+#define ELF_R_SYM   ELF64_R_SYM
+#define ELF_R_TYPE  ELF64_R_TYPE
+#define ELF_ST_BIND ELF64_ST_BIND
+#define ELF_ST_TYPE ELF64_ST_TYPE
+
+typedef elf64_ehdr_t elf_ehdr_t;
+typedef elf64_phdr_t elf_phdr_t;
+typedef elf64_dyn_t elf_dyn_t;
+typedef elf64_addr_t elf_addr_t;
+typedef elf64_off_t elf_off_t;
+typedef elf64_nhdr_t elf_nhdr_t;
+typedef elf64_auxv_t elf_auxv_t;
+typedef elf64_sym_t elf_sym_t;
+typedef elf64_rela_t elf_rela_t;
+typedef elf64_rel_t elf_rel_t;
+typedef elf64_relr_t elf_relr_t;
+
+enum {
+    R_NONE = 0,
+    R_64 = 1,
+    R_COPY = 5,
+    R_GLOB_DAT = 6,
+    R_JUMP_SLOT = 7,
+    R_RELATIVE = 8,
+    R_IRELATIVE = 37,
+};

arch/x86_64/include/bits/sched.h

@@ -1,36 +1,32 @@
 #pragma once
 
-#include <bits/types.h>
+#include <zinnia/types.h>
 #include <stdint.h>
 
 struct arch_task_context {
     uint64_t rsp;
     uint8_t* fpu_region;
+    phys_t fpu_phys;
     uint16_t ds, es, fs, gs;
     uint64_t fs_base, gs_base;
 };
 
-#define ARCH_ABI(typ, reg, ...) \
-    union { \
-        typ reg, __VA_ARGS__; \
-    }
-
 struct arch_context {
     uint64_t r15;
     uint64_t r14;
-    ARCH_ABI(uint64_t, r13, a7);
-    ARCH_ABI(uint64_t, r12, a6);
+    uint64_t r13;
+    uint64_t r12;
     uint64_t r11;
-    ARCH_ABI(uint64_t, r10, a5);
-    ARCH_ABI(uint64_t, r9, a3);
-    ARCH_ABI(uint64_t, r8, a4);
-    ARCH_ABI(uint64_t, rsi, a1);
-    ARCH_ABI(uint64_t, rdi, a0);
+    uint64_t r10;
+    uint64_t r9;
+    uint64_t r8;
+    uint64_t rsi;
+    uint64_t rdi;
     uint64_t rbp;
-    ARCH_ABI(uint64_t, rdx, a2, ret1);
+    uint64_t rdx;
     uint64_t rcx;
     uint64_t rbx;
-    ARCH_ABI(uint64_t, rax, num, ret0);
+    uint64_t rax;
     uint64_t isr;   // Pushed onto the stack by the interrupt handler stubs.
     uint64_t error; // Pushed onto the stack by the CPU if the interrupt has an error code.
     uint64_t rip;   // The rest is pushed onto the stack by the CPU during an interrupt.
@@ -40,16 +36,18 @@ struct arch_context {
     uint64_t ss;
 };
 
-static_assert(sizeof(struct arch_context) == 22 * sizeof(uint64_t));
-
 #define ARCH_CTX_NUM  rax
+#define ARCH_CTX_SP   rsp
 #define ARCH_CTX_A0   rdi
 #define ARCH_CTX_A1   rsi
 #define ARCH_CTX_A2   rdx
-#define ARCH_CTX_A3   r9
+#define ARCH_CTX_A3   r10
 #define ARCH_CTX_A4   r8
-#define ARCH_CTX_A5   r10
-#define ARCH_CTX_A6   r12
-#define ARCH_CTX_A7   r13
+#define ARCH_CTX_A5   r9
 #define ARCH_CTX_RET0 rax
 #define ARCH_CTX_RET1 rdx
+
+struct arch_syscall_restart {
+    uint64_t rax;
+    uint64_t rdx;
+};

arch/x86_64/include/bits/types.h

@@ -3,4 +3,3 @@
 #include <stdint.h>
 
 typedef uint64_t phys_t;
-typedef uint64_t reg_t;

arch/x86_64/include/x86_64/apic.h

@@ -0,0 +1,81 @@
+#pragma once
+
+#include <zinnia/mmio.h>
+#include <stdint.h>
+
+struct local_apic {
+    uint32_t id;
+    uint32_t ticks_per_10ms;
+    void* xapic_regs;
+};
+
+enum apic_delivery_mode {
+    APIC_DELIVERY_FIXED = 0b000,
+    APIC_DELIVERY_LOWESTPRIO = 0b001,
+    APIC_DELIVERY_SMI = 0b010,
+    APIC_DELIVERY_NMI = 0b100,
+    APIC_DELIVERY_INIT = 0b101,
+    APIC_DELIVERY_STARTUP = 0b110,
+};
+
+enum apic_dest_mode {
+    APIC_DEST_PHYSICAL = 0,
+    APIC_DEST_LOGICAL = 1,
+};
+
+enum apic_delivery_status {
+    APIC_DELIVERY_STATUS_IDLE = 0,
+    APIC_DELIVERY_STATUS_PENDING = 1,
+};
+
+enum apic_level {
+    APIC_LEVEL_DEASSERT = 0,
+    APIC_LEVEL_ASSERT = 1,
+};
+
+enum apic_trigger_mode {
+    APIC_TRIGGER_EDGE = 0,
+    APIC_TRIGGER_LEVEL = 1,
+};
+
+constexpr mmio_reg32 APIC_REG_ID = {.offset = 0x20};
+constexpr mmio_field32 APIC_ID_XAPIC = {APIC_REG_ID, 24, 8};
+constexpr mmio_reg32 APIC_REG_TPR = {.offset = 0x80};
+constexpr mmio_reg32 APIC_REG_EOI = {.offset = 0xB0};
+constexpr mmio_reg32 APIC_REG_LDR = {.offset = 0xD0};
+constexpr mmio_reg32 APIC_REG_DFR = {.offset = 0xE0};
+constexpr mmio_reg32 APIC_REG_SIVR = {.offset = 0xF0};
+constexpr mmio_field32 APIC_SIVR_VECTOR = {APIC_REG_SIVR, 0, 8};
+constexpr mmio_field32 APIC_SIVR_ENABLE = {APIC_REG_SIVR, 8, 1};
+constexpr mmio_reg32 APIC_REG_ESR = {.offset = 0x280};
+constexpr mmio_reg64 APIC_REG_ICR = {.offset = 0x300};
+constexpr mmio_field64 APIC_ICR_VECTOR = {APIC_REG_ICR, 0, 8};
+constexpr mmio_field64 APIC_ICR_DELIVERY_MODE = {APIC_REG_ICR, 8, 3};
+constexpr mmio_field64 APIC_ICR_DEST_MODE = {APIC_REG_ICR, 11, 1};
+constexpr mmio_field64 APIC_ICR_DELIVERY_STATUS = {APIC_REG_ICR, 12, 1};
+constexpr mmio_field64 APIC_ICR_LEVEL = {APIC_REG_ICR, 14, 1};
+constexpr mmio_field64 APIC_ICR_TRIGGER_MODE = {APIC_REG_ICR, 15, 1};
+constexpr mmio_field64 APIC_ICR_DEST_XAPIC = {APIC_REG_ICR, 56, 8};
+constexpr mmio_field64 APIC_ICR_DEST_X2APIC = {APIC_REG_ICR, 32, 32};
+constexpr mmio_reg32 APIC_REG_ICR_LO = {.offset = 0x300};
+constexpr mmio_reg32 APIC_REG_ICR_HI = {.offset = 0x310};
+constexpr mmio_reg32 APIC_REG_LVT_TR = {.offset = 0x320};
+constexpr mmio_field32 APIC_LVT_TR_VECTOR = {APIC_REG_LVT_TR, 0, 8};
+constexpr mmio_reg32 APIC_REG_ICR_TIMER = {.offset = 0x380};
+constexpr mmio_reg32 APIC_REG_CCR = {.offset = 0x390};
+constexpr mmio_reg32 APIC_REG_DCR = {.offset = 0x3E0};
+
+void lapic_init(struct local_apic* lapic);
+void lapic_eoi(struct local_apic* lapic);
+
+void lapic_send_ipi(
+    struct local_apic* lapic,
+    uint32_t target,
+    uint8_t vector,
+    enum apic_delivery_mode delivery_mode,
+    enum apic_dest_mode dest_mode,
+    enum apic_level level,
+    enum apic_trigger_mode trigger_mode
+);
+
+void pic_disable();

arch/x86_64/include/x86_64/asm.h

@@ -40,6 +40,12 @@ static inline void asm_wrxcr(uint32_t reg, uint64_t val) {
     asm volatile("xsetbv" ::"a"(eax), "d"(edx), "c"(reg) : "memory");
 }
 
+static inline uint64_t asm_rdxcr(uint32_t reg) {
+    uint32_t eax, edx;
+    asm volatile("xgetbv" : "=a"(eax), "=d"(edx) : "c"(reg));
+    return ((uint64_t)edx << 32) | eax;
+}
+
 // Saves the FPU state to a 512-byte region of memory using FXSAVE.
 // Pointer must be 16-byte aligned.
 static inline void asm_fxsave(void* mem) {
@@ -55,13 +61,13 @@ static inline void asm_fxrstor(const void* mem) {
 // Saves the FPU state to a region of memory using XSAVE.
 // Pointer must be 16-byte aligned.
 static inline void asm_xsave(void* mem) {
-    asm volatile("xsave [%0]" ::"r"(mem) : "memory");
+    asm volatile("xsave [%0]" ::"r"(mem), "a"(0xFFFF'FFFF), "d"(0xFFFF'FFFF) : "memory");
 }
 
 // Restores the FPU state from a region of memory using XRSTOR.
 // Pointer must be 16-byte aligned.
 static inline void asm_xrstor(const void* mem) {
-    asm volatile("xrstor [%0]" ::"r"(mem) : "memory");
+    asm volatile("xrstor [%0]" ::"r"(mem), "a"(0xFFFF'FFFF), "d"(0xFFFF'FFFF) : "memory");
 }
 
 static inline uint8_t asm_inb(uint16_t port) {

arch/x86_64/include/x86_64/defs.h

@@ -0,0 +1,255 @@
+#pragma once
+
+#include <stdint.h>
+
+enum : uint32_t {
+    CPUID_1C_SSE3 = 1u << 0,
+    CPUID_1C_PCLMUL = 1u << 1,
+    CPUID_1C_DTES64 = 1u << 2,
+    CPUID_1C_MONITOR = 1u << 3,
+    CPUID_1C_DS_CPL = 1u << 4,
+    CPUID_1C_VMX = 1u << 5,
+    CPUID_1C_SMX = 1u << 6,
+    CPUID_1C_EST = 1u << 7,
+    CPUID_1C_TM2 = 1u << 8,
+    CPUID_1C_SSSE3 = 1u << 9,
+    CPUID_1C_CID = 1u << 10,
+    CPUID_1C_SDBG = 1u << 11,
+    CPUID_1C_FMA = 1u << 12,
+    CPUID_1C_CX16 = 1u << 13,
+    CPUID_1C_XTPR = 1u << 14,
+    CPUID_1C_PDCM = 1u << 15,
+    CPUID_1C_PCID = 1u << 17,
+    CPUID_1C_DCA = 1u << 18,
+    CPUID_1C_SSE4_1 = 1u << 19,
+    CPUID_1C_SSE4_2 = 1u << 20,
+    CPUID_1C_X2APIC = 1u << 21,
+    CPUID_1C_MOVBE = 1u << 22,
+    CPUID_1C_POPCNT = 1u << 23,
+    CPUID_1C_TSC = 1u << 24,
+    CPUID_1C_AES = 1u << 25,
+    CPUID_1C_XSAVE = 1u << 26,
+    CPUID_1C_OSXSAVE = 1u << 27,
+    CPUID_1C_AVX = 1u << 28,
+    CPUID_1C_F16C = 1u << 29,
+    CPUID_1C_RDRAND = 1u << 30,
+    CPUID_1C_HYPERVISOR = 1u << 31,
+};
+
+enum : uint32_t {
+    CPUID_1D_FPU = 1u << 0,
+    CPUID_1D_VME = 1u << 1,
+    CPUID_1D_DE = 1u << 2,
+    CPUID_1D_PSE = 1u << 3,
+    CPUID_1D_TSC = 1u << 4,
+    CPUID_1D_MSR = 1u << 5,
+    CPUID_1D_PAE = 1u << 6,
+    CPUID_1D_MCE = 1u << 7,
+    CPUID_1D_CX8 = 1u << 8,
+    CPUID_1D_APIC = 1u << 9,
+    CPUID_1D_SEP = 1u << 11,
+    CPUID_1D_MTRR = 1u << 12,
+    CPUID_1D_PGE = 1u << 13,
+    CPUID_1D_MCA = 1u << 14,
+    CPUID_1D_CMOV = 1u << 15,
+    CPUID_1D_PAT = 1u << 16,
+    CPUID_1D_PSE36 = 1u << 17,
+    CPUID_1D_PSN = 1u << 18,
+    CPUID_1D_CLFLUSH = 1u << 19,
+    CPUID_1D_DS = 1u << 21,
+    CPUID_1D_ACPI = 1u << 22,
+    CPUID_1D_MMX = 1u << 23,
+    CPUID_1D_FXSR = 1u << 24,
+    CPUID_1D_SSE = 1u << 25,
+    CPUID_1D_SSE2 = 1u << 26,
+    CPUID_1D_SS = 1u << 27,
+    CPUID_1D_HTT = 1u << 28,
+    CPUID_1D_TM = 1u << 29,
+    CPUID_1D_IA64 = 1u << 30,
+    CPUID_1D_PBE = 1u << 31,
+};
+
+enum : uint32_t {
+    CPUID_7B_FSGSBASE = 1u << 0,
+    CPUID_7B_SGX = 1u << 2,
+    CPUID_7B_BMI = 1u << 3,
+    CPUID_7B_HLE = 1u << 4,
+    CPUID_7B_AVX2 = 1u << 5,
+    CPUID_7B_SMEP = 1u << 7,
+    CPUID_7B_BMI2 = 1u << 8,
+    CPUID_7B_RTM = 1u << 11,
+    CPUID_7B_AVX512F = 1u << 16,
+    CPUID_7B_AVX512DQ = 1u << 17,
+    CPUID_7B_RDSEED = 1u << 18,
+    CPUID_7B_ADX = 1u << 19,
+    CPUID_7B_SMAP = 1u << 20,
+    CPUID_7B_AVX512IFMA = 1u << 21,
+    CPUID_7B_CLFLUSHOPT = 1u << 23,
+    CPUID_7B_CLWB = 1u << 24,
+    CPUID_7B_AVX512CD = 1u << 28,
+    CPUID_7B_SHA = 1u << 29,
+    CPUID_7B_AVX512BW = 1u << 30,
+    CPUID_7B_AVX512VL = 1u << 31,
+};
+
+enum : uint32_t {
+    CPUID_7C_AVX512VBMI = 1u << 1,
+    CPUID_7C_UMIP = 1u << 2,
+    CPUID_7C_PKU = 1u << 3,
+    CPUID_7C_OSPKE = 1u << 4,
+    CPUID_7C_WAITPKG = 1u << 5,
+    CPUID_7C_AVX512VBMI2 = 1u << 6,
+    CPUID_7C_SHSTK = 1u << 7,
+    CPUID_7C_GFNI = 1u << 8,
+    CPUID_7C_VAES = 1u << 9,
+    CPUID_7C_VPCLMULQDQ = 1u << 10,
+    CPUID_7C_AVX512VNNI = 1u << 11,
+    CPUID_7C_AVX512BITALG = 1u << 12,
+    CPUID_7C_TME_EN = 1u << 13,
+    CPUID_7C_AVX512VPOPCNTDQ = 1u << 14,
+    CPUID_7C_RDPID = 1u << 22,
+    CPUID_7C_KL = 1u << 23,
+    CPUID_7C_CLDEMOTE = 1u << 25,
+    CPUID_7C_MOVDIRI = 1u << 27,
+    CPUID_7C_MOVDIR64B = 1u << 28,
+    CPUID_7C_ENQCMD = 1u << 29,
+};
+
+enum : uint32_t {
+    CPUID_7D_UINTR = 1u << 5,
+    CPUID_7D_AVX512VP2INTERSECT = 1u << 8,
+    CPUID_7D_SERIALIZE = 1u << 14,
+    CPUID_7D_TSXLDTRK = 1u << 16,
+    CPUID_7D_PCONFIG = 1u << 18,
+    CPUID_7D_IBT = 1u << 20,
+    CPUID_7D_AMX_BF16 = 1u << 22,
+    CPUID_7D_AVX512FP16 = 1u << 23,
+    CPUID_7D_AMX_TILE = 1u << 24,
+    CPUID_7D_AMX_INT8 = 1u << 25,
+};
+
+enum : uint64_t {
+    RFLAGS_CF = 1ull << 0,
+    RFLAGS_BRKI = 1ull << 1,
+    RFLAGS_PF = 1ull << 2,
+    RFLAGS_AF = 1ull << 4,
+    RFLAGS_ZF = 1ull << 6,
+    RFLAGS_SF = 1ull << 7,
+    RFLAGS_TF = 1ull << 8,
+    RFLAGS_IF = 1ull << 9,
+    RFLAGS_DF = 1ull << 10,
+    RFLAGS_OF = 1ull << 11,
+    RFLAGS_IOPL = 3ull << 12,
+    RFLAGS_NT = 1ull << 14,
+    RFLAGS_RF = 1ull << 16,
+    RFLAGS_VM = 1ull << 17,
+    RFLAGS_AC = 1ull << 18,
+    RFLAGS_VIF = 1ull << 19,
+    RFLAGS_VIP = 1ull << 20,
+    RFLAGS_ID = 1ull << 21,
+};
+
+enum : uint64_t {
+    XCR0_X87 = 1ull << 0,
+    XCR0_SSE = 1ull << 1,
+    XCR0_AVX = 1ull << 2,
+    XCR0_AXV512_OPMASK = 1ull << 5,
+    XCR0_AVX512_ZMM_HI256 = 1ull << 6,
+    XCR0_AVX512_HI16_ZMM = 1ull << 7,
+};
+
+enum : uint64_t {
+    CR0_PE = 1ull << 0,
+    CR0_MP = 1ull << 1,
+    CR0_EM = 1ull << 2,
+    CR0_TS = 1ull << 3,
+    CR0_ET = 1ull << 4,
+    CR0_NE = 1ull << 5,
+    CR0_WP = 1ull << 16,
+    CR0_AM = 1ull << 18,
+    CR0_NW = 1ull << 29,
+    CR0_CD = 1ull << 30,
+    CR0_PG = 1ull << 31,
+};
+
+enum : uint64_t {
+    CR4_VME = 1ull << 0,
+    CR4_PVI = 1ull << 1,
+    CR4_TSD = 1ull << 2,
+    CR4_DE = 1ull << 3,
+    CR4_PSE = 1ull << 4,
+    CR4_PAE = 1ull << 5,
+    CR4_MCE = 1ull << 6,
+    CR4_PGE = 1ull << 7,
+    CR4_PCE = 1ull << 8,
+    CR4_OSFXSR = 1ull << 9,
+    CR4_OSXMMEXCPT = 1ull << 10,
+    CR4_UMIP = 1ull << 11,
+    CR4_VMXE = 1ull << 13,
+    CR4_SMXE = 1ull << 14,
+    CR4_FSGSBASE = 1ull << 16,
+    CR4_PCIDE = 1ull << 17,
+    CR4_OSXSAVE = 1ull << 18,
+    CR4_SMEP = 1ull << 20,
+    CR4_SMAP = 1ull << 21,
+    CR4_PKE = 1ull << 22,
+    CR4_CET = 1ull << 23,
+    CR4_PKS = 1ull << 24,
+};
+
+enum : uint64_t {
+    MSR_EFER_SCE = 1ull << 0,
+    MSR_EFER_LME = 1ull << 8,
+    MSR_EFER_LMA = 1ull << 10,
+    MSR_EFER_NXE = 1ull << 11,
+    MSR_EFER_SVME = 1ull << 12,
+    MSR_EFER_LMSLE = 1ull << 13,
+    MSR_EFER_FFXSR = 1ull << 14,
+    MSR_EFER_TCE = 1ull << 15,
+};
+
+enum : uint32_t {
+    MSR_PAT = 0x277,
+    MSR_EFER = 0xC0000080,
+    MSR_STAR = 0xC0000081,
+    MSR_LSTAR = 0xC0000082,
+    MSR_CSTAR = 0xC0000083,
+    MSR_SFMASK = 0xC0000084,
+    MSR_FS_BASE = 0xC0000100,
+    MSR_GS_BASE = 0xC0000101,
+    MSR_KERNEL_GS_BASE = 0xC0000102,
+};
+
+enum : uint8_t {
+    PAT_UC = 0x0,
+    PAT_WC = 0x1,
+    PAT_WT = 0x4,
+    PAT_WP = 0x5,
+    PAT_WB = 0x6,
+    PAT_UCM = 0x7,
+};
+
+enum : uint8_t {
+    CPL_USER = 0x3,
+    CPL_KERNEL = 0x0,
+};
+
+enum : uint8_t {
+    IDT_DE = 0x0,
+    IDT_DB = 0x1,
+    IDT_BP = 0x3,
+    IDT_OF = 0x4,
+    IDT_BR = 0x5,
+    IDT_UD = 0x6,
+    IDT_NM = 0x7,
+    IDT_SS = 0xC,
+    IDT_GP = 0xD,
+    IDT_PF = 0xE,
+    IDT_MF = 0x10,
+    IDT_AC = 0x11,
+    IDT_XM = 0x13,
+    IDT_IPI_SHOOTDOWN = 0xFC,
+    IDT_TIMER = 0xFD,
+    IDT_SPURIOUS = 0xFE,
+    IDT_IPI_RESCHED = 0xFF,
+};

arch/x86_64/include/x86_64/gdt.h

@@ -1,6 +1,6 @@
 #pragma once
 
-#include <common/compiler.h>
+#include <zinnia/compiler.h>
 #include <stdint.h>
 
 union gdt_desc {
@@ -50,7 +50,7 @@ struct [[__packed]] gdtr {
     struct gdt* base;
 };
 
-struct percpu;
+extern const struct gdt gdt_base;
 
 // Initializes a GDT on the local CPU.
 void gdt_load();

arch/x86_64/include/x86_64/idt.h

@@ -1,6 +1,6 @@
 #pragma once
 
-#include <kernel/init.h>
+#include <zinnia/init.h>
 
 [[__init]]
 void idt_init();

arch/x86_64/include/x86_64/percpu.h

@@ -1,6 +1,7 @@
 #pragma once
 
-#include <kernel/irq.h>
+#include <zinnia/irq.h>
+#include <zinnia/percpu.h>
 #include <stddef.h>
 #include <x86_64/apic.h>
 #include <x86_64/gdt.h>
@@ -16,3 +17,8 @@ struct arch_percpu {
     void (*fpu_restore)(const void*);
     bool can_smap;
 };
+
+extern struct arch_percpu arch_data;
+
+// Initializes the calling CPU and makes `cpu` its per-CPU block.
+void x86_64_cpu_setup(struct percpu* cpu);

arch/x86_64/include/x86_64/pmap.h

@@ -0,0 +1,19 @@
+#pragma once
+#include <zinnia/pmap.h>
+
+enum : pte_t {
+    ARCH_FLAG_PRESENT = 1 << 0,
+    ARCH_FLAG_READ_WRITE = 1 << 1,
+    ARCH_FLAG_USER_MODE = 1 << 2,
+    ARCH_FLAG_WRITE_THROUGH = 1 << 3,
+    ARCH_FLAG_CACHE_DISABLE = 1 << 4,
+    ARCH_FLAG_ACCESSED = 1 << 5,
+    ARCH_FLAG_DIRTY = 1 << 6,
+    ARCH_FLAG_SIZE = 1 << 7,
+    ARCH_FLAG_GLOBAL = 1 << 8,
+    ARCH_FLAG_AVAILABLE = 1 << 9,
+    ARCH_FLAG_ATTRIBUTE_TABLE = 1 << 7,
+    ARCH_FLAG_EXECUTE_DISABLE = 1LU << 63,
+
+    ARCH_PTE_ADDR_MASK = 0x000F'FFFF'FFFF'F000,
+};

arch/x86_64/include/x86_64/smp.h

@@ -0,0 +1,24 @@
+#pragma once
+
+#include <zinnia/atomic.h>
+#include <zinnia/compiler.h>
+#include <zinnia/utils.h>
+#include <stdint.h>
+#include <x86_64/gdt.h>
+
+struct [[__packed]] smp_info {
+    struct gdt gdt;
+    struct gdtr gdtr;
+    uint32_t farjmp_offset;
+    uint32_t farjmp_segment;
+    uint32_t temp_stack;
+    uint32_t temp_cr3;
+    uint64_t entry;
+    uint64_t hhdm_offset;
+    uint64_t percpu;
+    uint32_t lapic_id;
+    atomic_bool booted;
+};
+
+// Discovers all APs and starts them.
+void x86_64_smp_init();

arch/x86_64/include/x86_64/tss.h

@@ -1,7 +1,7 @@
 #pragma once
 
-#include <common/compiler.h>
 #include <stdint.h>
+#include <zinnia/compiler.h>
 
 struct [[__packed]] tss {
     uint32_t reserved0;

arch/x86_64/irq.c

@@ -0,0 +1,93 @@
+#include <zinnia/alloc.h>
+#include <zinnia/assert.h>
+#include <zinnia/percpu.h>
+#include <zinnia/utils.h>
+#include <arch/irq.h>
+#include <stdint.h>
+#include <x86_64/apic.h>
+#include <x86_64/defs.h>
+#include <x86_64/percpu.h>
+
+bool arch_irq_get_state() {
+    uint64_t flags;
+    asm volatile("pushf; pop %0" : "=r"(flags)::"memory");
+    return flags & RFLAGS_IF;
+}
+
+bool arch_irq_set_state(bool state) {
+    bool old = arch_irq_get_state();
+    if (state)
+        asm volatile("sti" ::: "memory");
+    else
+        asm volatile("cli" ::: "memory");
+    return old;
+}
+
+void arch_irq_wait() {
+    asm volatile("hlt");
+}
+
+struct apic_msi_line {
+    struct msi_line msi;
+    uint8_t vector;
+    uint32_t lapic;
+};
+
+static phys_t apic_msi_msg_addr(struct msi_line* self) {
+    struct apic_msi_line* line = containerof(self, struct apic_msi_line, msi);
+    return 0xFEE0'0000 | ((phys_t)line->lapic << 12);
+}
+
+static uint32_t apic_msi_msg_data(struct msi_line* self) {
+    return containerof(self, struct apic_msi_line, msi)->vector;
+}
+
+static enum irq_mode apic_msi_set_config(
+    struct irq_line* self,
+    enum irq_trigger_mode trigger,
+    enum irq_polarity polarity
+) {
+    assert(trigger == IRQ_TRIGGER_EDGE, "MSIs must be edge triggered");
+    return IRQ_MODE_EOI;
+}
+
+static void apic_msi_mask(struct irq_line* self) {}
+
+static void apic_msi_unmask(struct irq_line* self) {}
+
+static void apic_msi_eoi(struct irq_line* self) {
+    lapic_eoi(&percpu_ref(arch_data)->lapic);
+}
+
+errno_t arch_irq_alloc_msi(struct msi_line** out) {
+    struct apic_msi_line* line = mem_alloc(sizeof(*line), 0);
+    if (!line)
+        return ENOMEM;
+
+    irq_lock();
+    struct arch_percpu* arch_cpu = percpu_ref(arch_data);
+    size_t slot;
+    for (slot = 0; slot < ARRAY_SIZE(arch_cpu->irq_lines); slot++) {
+        if (!arch_cpu->irq_lines[slot])
+            break;
+    }
+    if (slot == ARRAY_SIZE(arch_cpu->irq_lines)) {
+        irq_unlock();
+        mem_free(line);
+        return ENOSPC;
+    }
+
+    line->msi.line.set_config = apic_msi_set_config;
+    line->msi.line.mask = apic_msi_mask;
+    line->msi.line.unmask = apic_msi_unmask;
+    line->msi.line.eoi = apic_msi_eoi;
+    line->msi.msg_addr = apic_msi_msg_addr;
+    line->msi.msg_data = apic_msi_msg_data;
+    line->vector = slot + 0x20;
+    line->lapic = arch_cpu->lapic.id;
+    arch_cpu->irq_lines[slot] = &line->msi.line;
+    irq_unlock();
+
+    *out = &line->msi;
+    return 0;
+}

arch/x86_64/mem.c

@@ -1,4 +1,4 @@
-#include <kernel/types.h>
+#include <arch/mem.h>
 #include <stddef.h>
 #include <stdint.h>
 
@@ -29,3 +29,7 @@ uintptr_t arch_mem_pfndb_addr() {
 uintptr_t arch_mem_mapping_addr() {
     return 0xFFFF'C000'0000'0000;
 }
+
+bool arch_mem_addr_is_user(uintptr_t addr) {
+    return addr < 0x0000'7FFF'FFFF'F000;
+}

arch/x86_64/meson.build

@@ -1,11 +1,12 @@
 kernel_c_args += [
     '-mgeneral-regs-only',
     '-mno-red-zone',
-    '-mcmodel=kernel',
+    '-masm=intel',
 ]
 
 kernel_sources += files(
     'apic.c',
+    'archctl.c',
     'gdt.c',
     'hpet.c',
     'idt.c',
@@ -13,12 +14,20 @@ kernel_sources += files(
     'mem.c',
     'percpu.c',
     'pmap.c',
+    'random.c',
     'sched.c',
     'serial.c',
     'smp.c',
-    'sys.c',
+    'start.c',
     'syscall.c',
-    'trampoline.S',
     'tsc.c',
     'usercopy.c',
 )
+
+if kconfig.get('CONFIG_PCI', 'n') == 'y'
+    kernel_sources += files('pci.c')
+endif
+
+if kconfig.get('CONFIG_ACPI', 'n') == 'y'
+    kernel_sources += files('acpi.c')
+endif

arch/x86_64/pci.c

@@ -0,0 +1,50 @@
+#include <zinnia/init.h>
+#include <zinnia/pci.h>
+#include <zinnia/spin.h>
+#include <x86_64/asm.h>
+
+constexpr uint16_t PCI_CONFIG_ADDRESS = 0xcf8;
+constexpr uint16_t PCI_CONFIG_DATA = 0xcfc;
+
+static struct spinlock port_lock = {};
+
+static void port_select(const struct pci_address* addr, uint16_t offset) {
+    asm_outl(
+        PCI_CONFIG_ADDRESS,
+        1u << 31 | (uint32_t)addr->bus << 16 | (uint32_t)(addr->device & 0x1f) << 11 |
+            (uint32_t)(addr->function & 0x7) << 8 | (offset & 0xfc)
+    );
+}
+
+static uint32_t port_read32(struct pci_access*, const struct pci_address* addr, uint16_t offset) {
+    spin_lock(&port_lock);
+    port_select(addr, offset);
+    uint32_t value = asm_inl(PCI_CONFIG_DATA);
+    spin_unlock(&port_lock);
+    return value;
+}
+
+static void port_write32(struct pci_access*, const struct pci_address* addr, uint16_t offset, uint32_t value) {
+    spin_lock(&port_lock);
+    port_select(addr, offset);
+    asm_outl(PCI_CONFIG_DATA, value);
+    spin_unlock(&port_lock);
+}
+
+static struct pci_access port_access = {
+    .name = "port",
+    .domain = 0,
+    .start_bus = 0,
+    .end_bus = 255,
+    .priority = PCI_ACCESS_PRIO_LEGACY,
+    .read32 = port_read32,
+    .write32 = port_write32,
+};
+
+[[__init]]
+static void pci_x86_stage_init(struct boot_info*) {
+    pci_access_register(&port_access);
+}
+INIT_TASK(pci_x86_stage, "arch.x86_64.pci", pci_x86_stage_init);
+INIT_DEPENDS(pci_x86_stage, mem_stage);
+INIT_ENTAILS(pci_x86_stage, pci_stage);

arch/x86_64/percpu.c

@@ -1,12 +1,15 @@
-#include <kernel/percpu.h>
-#include <kernel/print.h>
+#include <zinnia/initgraph.h>
+#include <zinnia/percpu.h>
+#include <zinnia/print.h>
+#include <config.h>
 #include <stddef.h>
 #include <x86_64/apic.h>
 #include <x86_64/asm.h>
 #include <x86_64/defs.h>
 #include <x86_64/gdt.h>
-#include <x86_64/hpet.h>
 #include <x86_64/idt.h>
+#include <x86_64/percpu.h>
+#include <x86_64/smp.h>
 #include <x86_64/syscall.h>
 #include <x86_64/tsc.h>
 
@@ -38,22 +41,36 @@ union ia32_star {
 
 static_assert(sizeof(union ia32_star) == 8);
 
-static void setup_cpu(struct percpu* cpu) {
+[[__percpu]]
+struct arch_percpu arch_data = {0};
+
+void x86_64_cpu_setup(struct percpu* cpu) {
     asm_wrmsr(MSR_KERNEL_GS_BASE, 0);
     asm_wrmsr(MSR_GS_BASE, (uint64_t)cpu);
     asm_wrmsr(MSR_FS_BASE, 0);
 
+    struct arch_percpu* arch_cpu = percpu_ref(arch_data);
+
     gdt_load();
+
+    // TODO: not if FRED
     idt_load();
 
+    asm_wrmsr(
+        MSR_PAT,
+        PAT_WB | PAT_WT << 8 | PAT_UCM << 16 | PAT_UC << 24 | (uint64_t)PAT_WP << 32 | (uint64_t)PAT_WC << 40 |
+            (uint64_t)PAT_UCM << 48 | (uint64_t)PAT_UC << 56
+    );
+
     // Syscall extension.
     asm_wrmsr(MSR_EFER, asm_rdmsr(MSR_EFER) | MSR_EFER_SCE);
     union ia32_star star = {0};
     star.kernel_cs_ss = offsetof(struct gdt, kernel_code64);
-    star.user_cs_ss = offsetof(struct gdt, user_code32);
+    star.user_cs_ss = offsetof(struct gdt, user_code32) | CPL_USER;
     asm_wrmsr(MSR_STAR, star.value);
     asm_wrmsr(MSR_LSTAR, (uint64_t)arch_syscall_stub);
-    asm_wrmsr(MSR_SFMASK, RFLAGS_AC | RFLAGS_DF | RFLAGS_IF);
+    // Mask all RFLAGS except for BRKI which is reserved.
+    asm_wrmsr(MSR_SFMASK, ~RFLAGS_BRKI);
 
     // TODO: FRED
 
@@ -67,7 +84,7 @@ static void setup_cpu(struct percpu* cpu) {
 
     // Enable SSE.
     cr0 &= ~CR0_EM;
-    cr0 |= CR0_MP;
+    cr0 |= CR0_MP | CR0_WP;
     cr4 |= CR4_OSFXSR | CR4_OSXMMEXCPT;
 
     if (cpuid1.ecx & CPUID_1C_XSAVE) {
@@ -85,13 +102,13 @@ static void setup_cpu(struct percpu* cpu) {
 
         asm_wrxcr(0, xcr0);
 
-        cpu->arch.fpu_size = cpuid13.ecx;
-        cpu->arch.fpu_save = asm_xsave;
-        cpu->arch.fpu_restore = asm_xrstor;
+        arch_cpu->fpu_size = cpuid13.ecx;
+        arch_cpu->fpu_save = asm_xsave;
+        arch_cpu->fpu_restore = asm_xrstor;
     } else {
-        cpu->arch.fpu_size = 512;
-        cpu->arch.fpu_save = asm_fxsave;
-        cpu->arch.fpu_restore = asm_fxrstor;
+        arch_cpu->fpu_size = 512;
+        arch_cpu->fpu_save = asm_fxsave;
+        arch_cpu->fpu_restore = asm_fxrstor;
     }
 
     if (cpuid7.ecx & CPUID_7C_UMIP)
@@ -102,25 +119,27 @@ static void setup_cpu(struct percpu* cpu) {
 
     if (cpuid7.ebx & CPUID_7B_SMAP) {
         cr4 |= CR4_SMAP;
-        cpu->arch.can_smap = true;
+        arch_cpu->can_smap = true;
     }
 
     if (cpuid7.ebx & CPUID_7B_FSGSBASE)
         cr4 |= CR4_FSGSBASE;
 
-    asm volatile("mov %0, cr0" : "=r"(cr0));
-    asm volatile("mov %0, cr4" : "=r"(cr4));
+    asm volatile("mov cr0, %0" ::"r"(cr0));
+    asm volatile("mov cr4, %0" ::"r"(cr4));
 
-    lapic_init(&cpu->arch.lapic);
+    lapic_init(&arch_cpu->lapic);
     cpu->online = true;
 }
 
 void arch_percpu_init() {
-    hpet_init();
+#if CONFIG_TSC
     tsc_init();
+#endif
 
     // Init the BSP.
-    setup_cpu(&percpu_bsp);
+    x86_64_cpu_setup(&percpu_bsp);
 
     // Init any APs.
+    x86_64_smp_init();
 }

arch/x86_64/pmap.c

@@ -0,0 +1,95 @@
+#include <zinnia/irq.h>
+#include <zinnia/percpu.h>
+#include <zinnia/pmap.h>
+#include <zinnia/types.h>
+#include <x86_64/apic.h>
+#include <x86_64/defs.h>
+#include <x86_64/percpu.h>
+#include <x86_64/pmap.h>
+
+void pte_clear(pte_t* pte) {
+    *pte = 0;
+}
+
+void pte_write(pte_t* pte, pte_t val) {
+    *pte = val;
+}
+
+void pte_flush(uintptr_t vaddr) {
+    asm volatile("invlpg [%0]" ::"r"(vaddr) : "memory");
+}
+
+void pte_flush_all() {
+    uint64_t cr3;
+    asm volatile("mov %0, cr3" : "=r"(cr3));
+    asm volatile("mov cr3, %0" ::"r"(cr3) : "memory");
+}
+
+void pte_shootdown_kick(struct percpu* cpu) {
+    irq_lock();
+    lapic_send_ipi(
+        &percpu_ref(arch_data)->lapic,
+        percpu_ref_on(cpu, arch_data)->lapic.id,
+        IDT_IPI_SHOOTDOWN,
+        APIC_DELIVERY_FIXED,
+        APIC_DEST_PHYSICAL,
+        APIC_LEVEL_ASSERT,
+        APIC_TRIGGER_EDGE
+    );
+    irq_unlock();
+}
+
+pte_t pte_build(phys_t addr, enum pte_flags flags, enum cache_mode cache) {
+    pte_t result = ((pte_t)addr & ARCH_PTE_ADDR_MASK) | ARCH_FLAG_PRESENT;
+
+    if (flags & PTE_USER)
+        result |= ARCH_FLAG_USER_MODE;
+
+    if (flags & PTE_DIR)
+        result |= ARCH_FLAG_READ_WRITE;
+    else {
+        if (flags & PTE_WRITE)
+            result |= ARCH_FLAG_READ_WRITE;
+        if (!(flags & PTE_EXEC))
+            result |= ARCH_FLAG_EXECUTE_DISABLE;
+
+        switch (cache) {
+        case CACHE_ANY:
+        case CACHE_WRITE_BACK:
+            break;
+        case CACHE_WRITE_THROUGH:
+            result |= ARCH_FLAG_WRITE_THROUGH;
+            break;
+        case CACHE_MMIO:
+            result |= ARCH_FLAG_CACHE_DISABLE | ARCH_FLAG_WRITE_THROUGH;
+            break;
+        case CACHE_WRITE_COMBINE:
+            result |= ARCH_FLAG_ATTRIBUTE_TABLE | ARCH_FLAG_WRITE_THROUGH;
+            break;
+        }
+    }
+    return result;
+}
+
+pte_t pte_protect(pte_t old, enum pte_flags flags) {
+    pte_t result = old & ~(ARCH_FLAG_READ_WRITE | ARCH_FLAG_USER_MODE | ARCH_FLAG_EXECUTE_DISABLE);
+    if (flags & PTE_USER)
+        result |= ARCH_FLAG_USER_MODE;
+    if (flags & PTE_WRITE)
+        result |= ARCH_FLAG_READ_WRITE;
+    if (!(flags & PTE_EXEC))
+        result |= ARCH_FLAG_EXECUTE_DISABLE;
+    return result;
+}
+
+bool pte_is_present(pte_t* pte) {
+    return *pte & ARCH_FLAG_PRESENT;
+}
+
+phys_t pte_address(pte_t* pte) {
+    return (phys_t)(*pte & ARCH_PTE_ADDR_MASK);
+}
+
+void pmap_set(struct pmap* pt) {
+    asm volatile("mov cr3, %0" ::"r"(pt->root) : "memory");
+}

arch/x86_64/random.c

@@ -0,0 +1,36 @@
+#include <zinnia/initgraph.h>
+#include <zinnia/print.h>
+#include <zinnia/random.h>
+#include <x86_64/asm.h>
+
+#define CPUID_1C_RDRAND (1u << 30)
+#define RDRAND_RETRIES  10
+
+static bool rdrand_get_u64(struct random_source*, uint64_t* out) {
+    for (int i = 0; i < RDRAND_RETRIES; i++) {
+        uint64_t value;
+        uint8_t ok;
+        asm volatile("rdrand %0\n setc %1" : "=r"(value), "=qm"(ok) : : "cc");
+        if (ok) {
+            *out = value;
+            return true;
+        }
+    }
+    return false;
+}
+
+static struct random_source rdrand_source = {
+    .name = "x86_64.rdrand",
+    .quality = 100,
+    .get_u64 = rdrand_get_u64,
+};
+
+static void rdrand_init(struct boot_info*) {
+    if (asm_cpuid(1, 0).ecx & CPUID_1C_RDRAND) {
+        random_register(&rdrand_source);
+    } else {
+        log_warn("random: This CPU doesn't support RDRAND, ignoring\n");
+    }
+}
+INIT_TASK(rdrand_stage, "arch.x86_64.rdrand", rdrand_init);
+INIT_ENTAILS(rdrand_stage, random_stage);

arch/x86_64/sched.c

@@ -0,0 +1,272 @@
+#include <zinnia/alloc.h>
+#include <zinnia/assert.h>
+#include <zinnia/compiler.h>
+#include <zinnia/errno.h>
+#include <zinnia/irq.h>
+#include <zinnia/percpu.h>
+#include <zinnia/pmap.h>
+#include <zinnia/sched.h>
+#include <zinnia/vma.h>
+#include <arch/sched.h>
+#include <bits/sched.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+#include <x86_64/apic.h>
+#include <x86_64/asm.h>
+#include <x86_64/defs.h>
+#include <x86_64/gdt.h>
+#include <x86_64/idt.h>
+#include <x86_64/percpu.h>
+
+// The task frame consists of registers that the C ABI marks as callee-saved.
+// If we don't save them, these registers are lost during a context switch.
+struct task_frame {
+    uint64_t rbx, rbp, r12, r13, r14, r15, rip;
+};
+
+[[__naked]]
+static struct task* perform_switch(uint64_t* old_rsp, uint64_t new_rsp, struct task* prev) {
+    asm volatile(
+        "sub rsp, 0x30\n" // Make room for all regs (except RIP).
+        "mov [rsp + %c[rbx]], rbx\n"
+        "mov [rsp + %c[rbp]], rbp\n"
+        "mov [rsp + %c[r12]], r12\n"
+        "mov [rsp + %c[r13]], r13\n"
+        "mov [rsp + %c[r14]], r14\n"
+        "mov [rsp + %c[r15]], r15\n"
+        "mov [rdi], rsp\n" // rdi = old_rsp
+        "mov rsp, rsi\n"   // rsi = new_rsp
+        "mov rbx, [rsp + %c[rbx]]\n"
+        "mov rbp, [rsp + %c[rbp]]\n"
+        "mov r12, [rsp + %c[r12]]\n"
+        "mov r13, [rsp + %c[r13]]\n"
+        "mov r14, [rsp + %c[r14]]\n"
+        "mov r15, [rsp + %c[r15]]\n"
+        "add rsp, 0x30\n"
+        "mov rax, rdx\n"
+        "ret" // This will conveniently move us to the RIP we put at this stack entry.
+        :
+        : [rbx] "i"(offsetof(struct task_frame, rbx)),
+          [rbp] "i"(offsetof(struct task_frame, rbp)),
+          [r12] "i"(offsetof(struct task_frame, r12)),
+          [r13] "i"(offsetof(struct task_frame, r13)),
+          [r14] "i"(offsetof(struct task_frame, r14)),
+          [r15] "i"(offsetof(struct task_frame, r15))
+        : "memory"
+    );
+}
+
+struct task* arch_sched_switch(struct task* from, struct task* to) {
+    struct arch_percpu* cpu = percpu_ref(arch_data);
+    struct arch_task_context* from_ctx = &from->context;
+    struct arch_task_context* to_ctx = &to->context;
+
+    cpu->tss.rsp0 = kernel_stack_top(&to->kernel_stack);
+
+    if (from_ctx->fpu_region != nullptr) {
+        cpu->fpu_save(from_ctx->fpu_region);
+        from_ctx->ds = asm_read_ds();
+        from_ctx->es = asm_read_es();
+        from_ctx->fs = asm_read_fs();
+        from_ctx->gs = asm_read_gs();
+        from_ctx->fs_base = asm_rdmsr(MSR_FS_BASE);
+        from_ctx->gs_base = asm_rdmsr(MSR_KERNEL_GS_BASE);
+    }
+
+    if (to_ctx->fpu_region != nullptr) {
+        cpu->fpu_restore(to_ctx->fpu_region);
+        asm_write_ds(to_ctx->ds);
+        asm_write_es(to_ctx->es);
+        asm_write_fs(to_ctx->fs);
+
+        // If we have to change the GS segment we need to reload the MSR, otherwise we lose its value.
+        if (to_ctx->gs != asm_read_gs()) {
+            uint64_t percpu = asm_rdmsr(MSR_GS_BASE);
+            asm_write_gs(to_ctx->gs);
+            asm_wrmsr(MSR_GS_BASE, percpu);
+        }
+
+        asm_wrmsr(MSR_FS_BASE, to_ctx->fs_base);
+        asm_wrmsr(MSR_KERNEL_GS_BASE, to_ctx->gs_base);
+    }
+
+    return perform_switch(&from_ctx->rsp, to_ctx->rsp, from);
+}
+
+constexpr size_t FPU_FCW_OFFSET = 0;
+constexpr size_t FPU_MXCSR_OFFSET = 24;
+constexpr uint16_t FPU_DEFAULT_FCW = 0x37F;
+constexpr uint32_t FPU_DEFAULT_MXCSR = 0x1F80;
+
+// Calls task_entry with the correct parameters.
+[[__naked]]
+void task_entry_thunk() {
+    asm volatile(
+        "mov rdi, rbx\n"
+        "mov rsi, r12\n"
+        "mov rdx, rax\n"
+        "jmp task_entry"
+        :
+        :
+        : "memory", "rdi", "rsi", "rdx"
+    );
+}
+
+errno_t arch_task_init(
+    struct arch_task_context* context,
+    void* entry,
+    uintptr_t arg0,
+    uintptr_t stack_start,
+    bool is_user
+) {
+    struct arch_percpu* cpu = percpu_ref(arch_data);
+
+    assert((stack_start & 0xF) == 0, "Task stack is not 16-byte aligned!");
+
+    // Prepare a dummy stack with an entry point function to return to.
+    struct task_frame* frame = (struct task_frame*)(stack_start - sizeof(uint64_t)) - 1;
+    frame->rbx = (uint64_t)entry;
+    frame->r12 = arg0;
+    frame->rip = (uint64_t)task_entry_thunk;
+    context->rsp = (uint64_t)frame;
+
+    if (is_user) {
+        // Allocate FPU space.
+        const size_t fpu_size = cpu->fpu_size;
+        uintptr_t fpu_base = vm_alloc(fpu_size);
+        if (!fpu_base)
+            return ENOMEM;
+        phys_t pages;
+        errno_t s = mem_phys_alloc(ALIGN_UP(fpu_size, arch_mem_page_size()) / arch_mem_page_size(), 0, &pages);
+        if (s) {
+            vm_free(fpu_base, fpu_size);
+            return s;
+        }
+        for (size_t i = 0; i < fpu_size; i += arch_mem_page_size())
+            pmap_map(&kernel_vma.pmap, fpu_base + i, pages + i, PTE_WRITE | PTE_READ, CACHE_WRITE_BACK);
+        context->fpu_region = (void*)fpu_base;
+        context->fpu_phys = pages;
+
+        const uint16_t fcw = FPU_DEFAULT_FCW;
+        const uint32_t mxcsr = FPU_DEFAULT_MXCSR;
+        memcpy((uint8_t*)fpu_base + FPU_FCW_OFFSET, &fcw, sizeof(fcw));
+        memcpy((uint8_t*)fpu_base + FPU_MXCSR_OFFSET, &mxcsr, sizeof(mxcsr));
+
+        context->ds = asm_read_ds();
+        context->es = asm_read_es();
+        context->fs = asm_read_fs();
+        context->gs = asm_read_gs();
+        context->fs_base = asm_rdmsr(MSR_FS_BASE);
+        context->gs_base = asm_rdmsr(MSR_KERNEL_GS_BASE);
+    }
+
+    return 0;
+}
+
+void arch_task_fini(struct arch_task_context* context) {
+    if (context->fpu_region == nullptr)
+        return;
+
+    const size_t page_size = arch_mem_page_size();
+    const size_t fpu_size = percpu_ref(arch_data)->fpu_size;
+    const uintptr_t fpu_base = (uintptr_t)context->fpu_region;
+    for (size_t i = 0; i < fpu_size; i += page_size)
+        pmap_unmap(&kernel_vma.pmap, fpu_base + i);
+    pmap_shootdown(&kernel_vma.pmap);
+    mem_phys_free(context->fpu_phys, ALIGN_UP(fpu_size, page_size) / page_size);
+    vm_free(fpu_base, fpu_size);
+
+    context->fpu_region = nullptr;
+}
+
+void arch_task_fork(struct arch_task_context* dst) {
+    if (dst->fpu_region)
+        percpu_ref(arch_data)->fpu_save(dst->fpu_region);
+}
+
+void arch_context_init_user(struct arch_context* ctx, uintptr_t ip, uintptr_t sp) {
+    *ctx = (struct arch_context){
+        .rip = ip,
+        .rsp = sp,
+        .rflags = 0x202,
+        .cs = offsetof(struct gdt, user_code64) | CPL_USER,
+        .ss = offsetof(struct gdt, user_data) | CPL_USER,
+    };
+}
+
+[[__naked]]
+void arch_sched_preempt_disable() {
+    asm volatile(
+        "inc qword ptr gs:%c0\n"
+        "ret"
+        :
+        : "i"(offsetof(struct percpu, sched.preempt_level))
+    );
+}
+
+[[__naked]]
+bool arch_sched_preempt_enable() {
+    asm volatile(
+        "dec qword ptr gs:%c0\n"
+        "setz al\n"
+        "movzx eax, al\n"
+        "ret\n"
+        :
+        : "i"(offsetof(struct percpu, sched.preempt_level))
+        : "cc"
+    );
+}
+
+void arch_sched_kick(struct percpu* cpu) {
+    if (!cpu->online)
+        return;
+    // The xAPIC ICR takes two writes, which must not be interleaved with an IPI sent by an interrupt handler.
+    irq_lock();
+    lapic_send_ipi(
+        &percpu_ref(arch_data)->lapic,
+        percpu_ref_on(cpu, arch_data)->lapic.id,
+        IDT_IPI_RESCHED,
+        APIC_DELIVERY_FIXED,
+        APIC_DEST_PHYSICAL,
+        APIC_LEVEL_ASSERT,
+        APIC_TRIGGER_EDGE
+    );
+    irq_unlock();
+}
+
+[[__naked]]
+void arch_sched_jump_to_context(struct arch_context* context) {
+    asm volatile(
+        "mov rsp, rdi\n"
+        "jmp %0\n" ::"r"(interrupt_return)
+    );
+}
+
+void arch_sched_jump_to_user(uintptr_t ip, uintptr_t sp, uintptr_t arg) {
+    struct arch_context context = {
+        .rip = ip,
+        .rsp = sp,
+        .rdi = arg,
+        .rflags = 0x202,
+        .cs = offsetof(struct gdt, user_code64) | CPL_USER,
+        .ss = offsetof(struct gdt, user_data) | CPL_USER,
+    };
+
+    uintptr_t percpu = asm_rdmsr(MSR_GS_BASE);
+    asm volatile(
+        "mov ds, %0\n"
+        "mov es, %0\n"
+        "mov fs, %0\n"
+        "mov gs, %0\n"
+        :
+        : "a"(0)
+        : "memory"
+    );
+
+    asm_wrmsr(MSR_FS_BASE, 0);
+    asm_wrmsr(MSR_GS_BASE, percpu);
+    asm_wrmsr(MSR_KERNEL_GS_BASE, 0);
+
+    arch_sched_jump_to_context(&context);
+}

arch/x86_64/serial.c

@@ -1,4 +1,7 @@
-#include <kernel/console.h>
+#include <zinnia/console.h>
+#include <zinnia/init.h>
+#include <zinnia/initgraph.h>
+#include <arch/cpu.h>
 #include <stdint.h>
 #include <x86_64/asm.h>
 
@@ -11,7 +14,7 @@ static bool is_ready() {
 static void serial_write(struct console* con, const char* buf, size_t count) {
     for (size_t i = 0; i < count; i++) {
         while (!is_ready())
-            asm volatile("pause");
+            arch_cpu_pause();
 
         asm_outb(COM1_BASE, buf[i]);
     }
@@ -44,4 +47,10 @@ static struct console serial_con = {
     .write = serial_write,
     .init = serial_setup,
 };
-DEFINE_CONSOLE(&serial_con);
+
+[[__init]]
+static void serial_init(struct boot_info*) {
+    console_register(&serial_con);
+}
+INIT_TASK(serial_stage, "arch.x86_64.serial", serial_init);
+INIT_ENTAILS(serial_stage, console_stage);

arch/x86_64/smp.c

@@ -0,0 +1,359 @@
+#define pr_fmt(fmt) "smp: " fmt
+
+#include <zinnia/alloc.h>
+#include <zinnia/assert.h>
+#include <zinnia/atomic.h>
+#include <zinnia/clock.h>
+#include <zinnia/compiler.h>
+#include <zinnia/irq.h>
+#include <zinnia/percpu.h>
+#include <zinnia/pmap.h>
+#include <zinnia/print.h>
+#include <zinnia/sched.h>
+#include <zinnia/types.h>
+#include <zinnia/utils.h>
+#include <zinnia/vma.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+#include <uacpi/acpi.h>
+#include <uacpi/tables.h>
+#include <x86_64/apic.h>
+#include <x86_64/defs.h>
+#include <x86_64/percpu.h>
+#include <x86_64/pmap.h>
+#include <x86_64/smp.h>
+
+extern uint8_t smp_trampoline_start[];
+extern uint8_t smp_trampoline_data[];
+extern uint8_t smp_trampoline_end[];
+
+[[__naked, __used]]
+static void smp_trampoline() {
+    asm volatile(
+        ".pushsection .rodata\n"
+        ".code16\n"
+        ".global smp_trampoline_start\n"
+        "smp_trampoline_start:\n"
+        "    cli\n"
+        "    cld\n"
+        "    jmp .Lmode16\n"
+
+        ".org smp_trampoline_start + %c[data_off]\n"
+        ".global smp_trampoline_data\n"
+        "smp_trampoline_data:\n"
+        "    .skip %c[info_size]\n"
+
+        ".set .Ldata_offset, %c[data_off]\n"
+        ".set .Lgdtr_offset, (.Ldata_offset + %c[gdtr])\n"
+        ".set .Lfarjmp_offset, (.Ldata_offset + %c[farjmp])\n"
+        ".set .Ltemp_stack_offset, (.Ldata_offset + %c[temp_stack])\n"
+        ".set .Ltemp_cr3_offset, (.Ldata_offset + %c[temp_cr3])\n"
+        ".set .Lentry_offset, (.Ldata_offset + %c[entry])\n"
+        ".set .Lhhdm_offset, (.Ldata_offset + %c[hhdm])\n"
+        ".set .Linvalid_idtr_offset, (.Linvalid_idtr - smp_trampoline_start)\n"
+        ".set .Lmode32_offset, (.Lmode32 - smp_trampoline_start)\n"
+        ".set .Lmode64_offset, (.Lmode64 - smp_trampoline_start)\n"
+
+        ".Lmode16:\n"
+        "    mov bx, cs\n"
+        "    shl ebx, 4\n"
+
+        "    lidtd cs:.Linvalid_idtr_offset\n"
+        "    lgdtd cs:.Lgdtr_offset\n"
+
+        "    lea eax, [ebx + .Lmode32_offset]\n"
+        "    mov dword ptr cs:.Lfarjmp_offset, eax\n"
+
+        "    mov eax, %c[cr0]\n"
+        "    mov cr0, eax\n"
+        "    jmp fword ptr cs:.Lfarjmp_offset\n"
+
+        ".code32\n"
+        ".Lmode32:\n"
+        "    mov ax, %c[kernel32_ds]\n"
+        "    mov ds, ax\n"
+        "    mov es, ax\n"
+        "    mov fs, ax\n"
+        "    mov gs, ax\n"
+        "    mov ss, ax\n"
+
+        "    xor eax, eax\n"
+        "    lldt ax\n"
+
+        "    mov esp, dword ptr [ebx + .Ltemp_stack_offset]\n"
+
+        "    xor eax, eax\n"
+        "    mov cr4, eax\n"
+
+        "    or eax, %c[cr4_pae]\n"
+        "    mov cr4, eax\n"
+
+        "    mov ecx, %c[msr_efer]\n"
+        "    mov eax, %c[efer_lme]\n"
+        "    xor edx, edx\n"
+        "    wrmsr\n"
+
+        "    mov eax, dword ptr [ebx + .Ltemp_cr3_offset]\n"
+        "    mov cr3, eax\n"
+
+        "    mov eax, cr0\n"
+        "    or eax, %c[cr0_pg]\n"
+        "    mov cr0, eax\n"
+
+        "    lea eax, [ebx + .Lmode64_offset]\n"
+        "    push %c[kernel64_cs]\n"
+        "    push eax\n"
+        "    retf\n"
+
+        ".code64\n"
+        ".Lmode64:\n"
+        "    mov ax, %c[kernel64_ds]\n"
+        "    mov ds, ax\n"
+        "    mov es, ax\n"
+        "    mov fs, ax\n"
+        "    mov gs, ax\n"
+        "    mov ss, ax\n"
+
+        "    mov ecx, %c[msr_efer]\n"
+        "    rdmsr\n"
+        "    or eax, %c[efer_nxe]\n"
+        "    wrmsr\n"
+
+        "    xor ebp, ebp\n"
+
+        "    lea rdi, [rbx + .Ldata_offset]\n"
+        "    mov rax, [rbx + .Lentry_offset]\n"
+        "    add rsp, [rbx + .Lhhdm_offset]\n"
+        "    jmp rax\n"
+
+        ".Linvalid_idtr:\n"
+        "    .word 0\n"
+        "    .quad 0\n"
+
+        ".global smp_trampoline_end\n"
+        "smp_trampoline_end:\n"
+        ".popsection\n"
+        "    ud2\n"
+        :
+        : [data_off] "i"(8),
+          [info_size] "i"(sizeof(struct smp_info)),
+          [gdtr] "i"(offsetof(struct smp_info, gdtr)),
+          [farjmp] "i"(offsetof(struct smp_info, farjmp_offset)),
+          [temp_stack] "i"(offsetof(struct smp_info, temp_stack)),
+          [temp_cr3] "i"(offsetof(struct smp_info, temp_cr3)),
+          [entry] "i"(offsetof(struct smp_info, entry)),
+          [hhdm] "i"(offsetof(struct smp_info, hhdm_offset)),
+          [kernel32_ds] "i"(offsetof(struct gdt, kernel_data32)),
+          [kernel64_cs] "i"(offsetof(struct gdt, kernel_code64)),
+          [kernel64_ds] "i"(offsetof(struct gdt, kernel_data64)),
+          [cr0] "i"(CR0_PE | CR0_ET),
+          [cr0_pg] "i"((uint32_t)CR0_PG),
+          [cr4_pae] "i"(CR4_PAE),
+          [msr_efer] "i"(MSR_EFER),
+          [efer_lme] "i"(MSR_EFER_LME),
+          [efer_nxe] "i"(MSR_EFER_NXE)
+    );
+}
+
+constexpr size_t AP_BOOT_STACK_SIZE = 0x8000;
+constexpr uint64_t AP_BOOT_TIMEOUT_NS = 1'000'000'000;
+
+[[noreturn]]
+static void ap_entry(phys_t info_addr) {
+    // We're still running on the temporary page table.
+    pmap_set(&kernel_vma.pmap);
+
+    struct smp_info* info = HHDM_PTR(info_addr);
+    struct percpu* cpu = (struct percpu*)info->percpu;
+
+    x86_64_cpu_setup(cpu);
+    irq_lock();
+
+    // This task keeps running on the boot stack, but is never scheduled again after the first yield.
+    sched_init(&cpu->sched);
+
+    // Let the BSP know that we're alive.
+    // `info` must not be touched after this point.
+    atomic_store(&info->booted, 1, ATOMIC_RELEASE);
+
+    log("CPU %zu online\n", cpu->id);
+
+    sched_yield(&cpu->sched);
+    unreachable();
+}
+
+static bool start_ap(phys_t trampoline, uint32_t temp_cr3, uint32_t lapic_id) {
+    const size_t trampoline_size = smp_trampoline_end - smp_trampoline_start;
+
+    phys_t stack;
+    if (mem_phys_alloc(AP_BOOT_STACK_SIZE / arch_mem_page_size(), ALLOC_MEM32 | ALLOC_NOZERO, &stack)) {
+        log_err("Failed to allocate a boot stack for LAPIC %u\n", lapic_id);
+        return false;
+    }
+
+    struct percpu* cpu = percpu_new();
+    if (!cpu) {
+        log_err("Failed to allocate per-CPU data for LAPIC %u\n", lapic_id);
+        mem_phys_free(stack, AP_BOOT_STACK_SIZE / arch_mem_page_size());
+        return false;
+    }
+
+    log("Starting CPU %zu\n", cpu->id);
+
+    memcpy(HHDM_PTR(trampoline), smp_trampoline_start, trampoline_size);
+
+    const phys_t info_addr = trampoline + (smp_trampoline_data - smp_trampoline_start);
+    struct smp_info* info = HHDM_PTR(info_addr);
+    memcpy(&info->gdt, &gdt_base, sizeof(info->gdt));
+    info->gdtr.limit = sizeof(struct gdt) - 1;
+    info->gdtr.base = (struct gdt*)(info_addr + offsetof(struct smp_info, gdt));
+    info->farjmp_offset = 0; // Filled in by the trampoline.
+    info->farjmp_segment = offsetof(struct gdt, kernel_code32);
+    info->temp_stack = stack + AP_BOOT_STACK_SIZE;
+    info->temp_cr3 = temp_cr3;
+    info->entry = (uint64_t)ap_entry;
+    info->hhdm_offset = mem_hhdm_base;
+    info->percpu = (uint64_t)cpu;
+    info->lapic_id = lapic_id;
+    atomic_init(&info->booted, 0);
+
+    struct local_apic* lapic = &percpu_ref(arch_data)->lapic;
+
+    lapic_send_ipi(lapic, lapic_id, 0, APIC_DELIVERY_INIT, APIC_DEST_PHYSICAL, APIC_LEVEL_ASSERT, APIC_TRIGGER_EDGE);
+    clock_spin_ns(10'000'000);
+
+    lapic_send_ipi(
+        lapic,
+        lapic_id,
+        trampoline >> 12,
+        APIC_DELIVERY_STARTUP,
+        APIC_DEST_PHYSICAL,
+        APIC_LEVEL_ASSERT,
+        APIC_TRIGGER_EDGE
+    );
+    clock_spin_ns(10'000'000);
+
+    for (uint64_t waited = 0; !atomic_load(&info->booted, ATOMIC_ACQUIRE); waited += 1'000'000) {
+        if (waited >= AP_BOOT_TIMEOUT_NS) {
+            // The per-CPU data and boot stack are leaked on purpose, in case the AP still comes up.
+            log_err("CPU %zu (LAPIC %u) did not respond\n", cpu->id, lapic_id);
+            return false;
+        }
+        clock_spin_ns(1'000'000);
+    }
+
+    return true;
+}
+
+static errno_t build_temp_table(phys_t* out) {
+    const size_t pgsz = arch_mem_page_size();
+
+    phys_t mem;
+    errno_t status = mem_phys_alloc(6, ALLOC_MEM32, &mem);
+    if (status)
+        return status;
+
+    uint64_t* l4 = HHDM_PTR(mem);
+    uint64_t* l3 = HHDM_PTR(mem + pgsz);
+    const phys_t l2_base = mem + 2 * pgsz;
+
+    // Use 2 MiB pages.
+    l4[0] = (mem + pgsz) | ARCH_FLAG_PRESENT | ARCH_FLAG_READ_WRITE;
+    for (size_t i = 0; i < 4; i++) {
+        uint64_t* l2 = HHDM_PTR(l2_base + i * pgsz);
+        l3[i] = (l2_base + i * pgsz) | ARCH_FLAG_PRESENT | ARCH_FLAG_READ_WRITE;
+        for (size_t j = 0; j < 512; j++)
+            l2[j] = ((i << 30) + (j << 21)) | ARCH_FLAG_PRESENT | ARCH_FLAG_READ_WRITE | ARCH_FLAG_SIZE;
+    }
+
+    // Copy over the higher half from the kernel page table.
+    const uint64_t* kernel_l4 = HHDM_PTR(kernel_vma.pmap.root);
+    for (size_t i = 256; i < 512; i++)
+        l4[i] = kernel_l4[i];
+
+    *out = mem;
+    return 0;
+}
+
+void x86_64_smp_init() {
+    const size_t trampoline_size = smp_trampoline_end - smp_trampoline_start;
+    assert(trampoline_size <= arch_mem_page_size(), "SMP trampoline doesn't fit in a page");
+
+    const size_t max_cpus = percpu_max_cpus();
+    if (max_cpus <= 1)
+        return;
+
+    uacpi_table table;
+    if (uacpi_table_find_by_signature(ACPI_MADT_SIGNATURE, &table) != UACPI_STATUS_OK) {
+        log_warn("No MADT found, not starting any APs\n");
+        return;
+    }
+
+    phys_t trampoline;
+    if (mem_phys_alloc(1, ALLOC_MEM20, &trampoline)) {
+        log_err("Failed to allocate 20-bit memory for the AP trampoline\n");
+        uacpi_table_unref(&table);
+        return;
+    }
+
+    phys_t temp_table;
+    if (build_temp_table(&temp_table)) {
+        log_err("Failed to allocate a temporary page table\n");
+        mem_phys_free(trampoline, 1);
+        uacpi_table_unref(&table);
+        return;
+    }
+
+    const uint32_t bsp_id = percpu_ref(arch_data)->lapic.id;
+    bool all_booted = true;
+    size_t num_cpus = 1;
+
+    const struct acpi_madt* madt = table.ptr;
+    const uint8_t* entry = (const uint8_t*)madt->entries;
+    const uint8_t* end = (const uint8_t*)madt + madt->hdr.length;
+
+    while (entry + sizeof(struct acpi_entry_hdr) <= end && num_cpus < max_cpus) {
+        const struct acpi_entry_hdr* hdr = (const struct acpi_entry_hdr*)entry;
+
+        // Don't trust malformed firmware tables.
+        if (hdr->length < sizeof(struct acpi_entry_hdr) || entry + hdr->length > end) {
+            log_warn("MADT contains a malformed entry\n");
+            break;
+        }
+
+        uint32_t lapic_id = 0;
+        bool enabled = false;
+        switch (hdr->type) {
+        case ACPI_MADT_ENTRY_TYPE_LAPIC:
+            const struct acpi_madt_lapic* lapic = (const struct acpi_madt_lapic*)hdr;
+            lapic_id = lapic->id;
+            enabled = lapic->flags & ACPI_PIC_ENABLED;
+            break;
+        case ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC:
+            const struct acpi_madt_x2apic* x2apic = (const struct acpi_madt_x2apic*)hdr;
+            lapic_id = x2apic->id;
+            enabled = x2apic->flags & ACPI_PIC_ENABLED;
+            break;
+        }
+
+        if (enabled && lapic_id != bsp_id) {
+            if (start_ap(trampoline, temp_table, lapic_id))
+                num_cpus++;
+            else
+                all_booted = false;
+        }
+
+        entry += hdr->length;
+    }
+
+    uacpi_table_unref(&table);
+
+    // An AP which didn't respond might still be using these.
+    if (all_booted) {
+        mem_phys_free(temp_table, 6);
+        mem_phys_free(trampoline, 1);
+    }
+
+    log("%zu CPU(s) online\n", num_cpus);
+}

arch/x86_64/start.c

@@ -0,0 +1,19 @@
+#include <zinnia/compiler.h>
+#include <zinnia/errno.h>
+#include <zinnia/init.h>
+#include <zinnia/percpu.h>
+#include <uapi/archctl.h>
+#include <x86_64/apic.h>
+#include <x86_64/asm.h>
+#include <x86_64/defs.h>
+#include <x86_64/gdt.h>
+
+[[__init, __naked, __used]]
+void _start() {
+    asm volatile(
+        "mov rsp, %0\n"
+        "jmp %1"
+        :
+        : "r"(__ld_stack_top), "r"(kernel_entry)
+    );
+}

arch/x86_64/syscall.c

@@ -0,0 +1,73 @@
+#include <zinnia/compiler.h>
+#include <zinnia/percpu.h>
+#include <zinnia/syscall.h>
+#include <bits/sched.h>
+#include <stddef.h>
+#include <x86_64/defs.h>
+#include <x86_64/gdt.h>
+
+// TODO: Refactor to only push callee-saved registers.
+
+[[__naked]]
+void arch_syscall_stub() {
+    asm volatile(
+        "    swapgs\n"
+        "    mov gs:%c[user_stack], rsp\n"
+        "    mov rsp, gs:%c[kernel_stack]\n"
+        "    cld\n"
+        "1:\n"
+        "    push %c[user_data]\n" // ss
+        "    push gs:%c[user_stack]\n"
+        "    push r11\n"             // rflags
+        "    push %c[user_code64]\n" // cs
+        "    push rcx\n"             // rip
+        "    push 0x00\n"            // arch_context::error
+        "    push 0x00\n"            // arch_context::isr
+        "    push rax\n"
+        "    push rbx\n"
+        "    push rcx\n"
+        "    push rdx\n"
+        "    push rbp\n"
+        "    push rdi\n"
+        "    push rsi\n"
+        "    push r8\n"
+        "    push r9\n"
+        "    push r10\n"
+        "    push r11\n"
+        "    push r12\n"
+        "    push r13\n"
+        "    push r14\n"
+        "    push r15\n"
+        "    xor rbp, rbp\n"
+        "    mov rdi, rsp\n"          // SysV ABI first argument.
+        "    call syscall_dispatch\n" // Call syscall handler.
+        "    cli\n"
+        "    pop r15\n"
+        "    pop r14\n"
+        "    pop r13\n"
+        "    pop r12\n"
+        "    pop r11\n"
+        "    pop r10\n"
+        "    pop r9\n"
+        "    pop r8\n"
+        "    pop rsi\n"
+        "    pop rdi\n"
+        "    pop rbp\n"
+        "    pop rdx\n"
+        "    pop rcx\n"
+        "    pop rbx\n"
+        "    pop rax\n"
+        "    add rsp, 0x10\n" // Skip .error and .isr fields
+        "    pop rcx\n"       // rip
+        "    add rsp, 0x08\n" // Skip cs
+        "    pop r11\n"       // rflags
+        "    pop rsp\n"       // rsp
+        "    swapgs\n"
+        "    sysretq\n"
+        :
+        : [user_stack] "i"(offsetof(struct percpu, user_stack)),
+          [kernel_stack] "i"(offsetof(struct percpu, kernel_stack)),
+          [user_code64] "i"(offsetof(struct gdt, user_code64) | CPL_USER),
+          [user_data] "i"(offsetof(struct gdt, user_data) | CPL_USER)
+    );
+}

arch/x86_64/tsc.c

@@ -0,0 +1,88 @@
+#define pr_fmt(fmt) "x86_64/tsc: " fmt
+#include <zinnia/clock.h>
+#include <zinnia/cmdline.h>
+#include <zinnia/print.h>
+#include <zinnia/utils.h>
+#include <stdint.h>
+#include <x86_64/asm.h>
+#include <x86_64/defs.h>
+
+static bool use_tsc = true;
+static void tsc_option(bool opt) {
+    use_tsc = opt;
+}
+CMDLINE_OPTION("x86_64.tsc", "Enable timestamp counter", tsc_option);
+
+constexpr uint64_t nanos_per_sec = 1'000'000'000;
+static uint64_t tsc_freq = 0;
+static uint64_t tsc_base_cycles = 0;
+
+static uint64_t cycles_to_ns(uint64_t cycles, uint64_t freq) {
+    uint64_t seconds = cycles / freq;
+    uint64_t remaining_cycles = cycles % freq;
+    uint64_t fractional_ns = (uint64_t)((__uint128_t)remaining_cycles * (__uint128_t)nanos_per_sec / (__uint128_t)freq);
+    uint64_t ns = seconds * nanos_per_sec + fractional_ns;
+
+    return MIN(ns, UINT64_MAX);
+}
+
+static void tsc_reset(struct clock* clock) {
+    tsc_base_cycles = asm_rdtsc();
+}
+
+static uint64_t tsc_get_elapsed_ns(struct clock* clock) {
+    uint64_t cycles = asm_rdtsc() - tsc_base_cycles;
+    return cycles_to_ns(cycles, tsc_freq);
+}
+
+static struct clock tsc_clock = {
+    .name = "tsc",
+    .priority = 255,
+    .reset = tsc_reset,
+    .get_elapsed_ns = tsc_get_elapsed_ns,
+};
+
+void tsc_init() {
+    if (!use_tsc) {
+        log_warn("TSC disabled on the command line");
+        return;
+    }
+
+    if (!(asm_cpuid(1, 0).edx & CPUID_1D_TSC) || !(asm_cpuid(0x8000'0007, 0).edx & (1 << 8))) {
+        log_warn("No invariant TSC detected!\n");
+        return;
+    }
+
+    // Check for the TSC info leaf.
+    bool has_tsc_leaf = false;
+    struct cpuid tsc_leaf = {0};
+    if (asm_cpuid(0, 0).eax >= 0x15) {
+        tsc_leaf = asm_cpuid(0x15, 0);
+        has_tsc_leaf = true;
+    }
+
+    if (clock_available()) {
+        // Calibrate using existing clock.
+        uint64_t t1 = asm_rdtsc();
+        clock_spin_ns(10'000'000);
+        uint64_t t2 = asm_rdtsc();
+        tsc_freq = (t2 - t1) * 100;
+    } else if (has_tsc_leaf) {
+        // If we have no timer (yet), the only way we can calibrate the TSC is if CPUID gives us the frequency.
+        // On a normal system, this should usually never be called and is a last resort
+        // since at this point we have at least the HPET timer.
+        if (tsc_leaf.ecx != 0 && tsc_leaf.ebx != 0 && tsc_leaf.eax != 0) {
+            log("Calibrating TSC using CPUID 0x15");
+            tsc_freq = (uint64_t)tsc_leaf.ecx * tsc_leaf.ebx / tsc_leaf.eax;
+        } else {
+            log_err("Unable to calibrate TSC using CPUID frequency information");
+            return;
+        }
+    } else {
+        log_err("Unable to calibrate the TSC without a clock or static frequency info!\n");
+        return;
+    }
+
+    log("Timer frequency is %lu MHz\n", tsc_freq / 1'000'000);
+    clock_switch(&tsc_clock);
+}

arch/x86_64/usercopy.c

@@ -0,0 +1,142 @@
+#include <zinnia/compiler.h>
+#include <zinnia/percpu.h>
+#include <arch/usercopy.h>
+#include <x86_64/percpu.h>
+
+void arch_usercopy_allow(bool state) {
+    if (!percpu_ref(arch_data)->can_smap)
+        return;
+
+    if (state) {
+        asm volatile("stac" ::: "memory");
+    } else {
+        asm volatile("clac" ::: "memory");
+    }
+}
+
+extern void x86_64_read_start();
+extern void x86_64_read_end();
+extern void x86_64_read_fault();
+
+static const struct usercopy_region read_region = {
+    .start_ip = x86_64_read_start,
+    .end_ip = x86_64_read_end,
+    .fault_ip = x86_64_read_fault,
+};
+
+[[__naked]]
+bool arch_usercopy_read(void* dst, const __user void* src, size_t len, struct usercopy_region** region) {
+    asm volatile(
+        // Setup regs for `rep movsb`.
+        "    xchg rcx, rdx\n"
+        "    lea rax, [rip + %0]\n"
+        "    xchg [rdx], rax\n"
+
+        ".global x86_64_read_start\n"
+        "    x86_64_read_start:\n"
+        "    rep movsb\n"
+
+        ".global x86_64_read_end\n"
+        "x86_64_read_end:\n"
+        "    xor rax, rax\n"
+        "    xchg [rdx], rax\n"
+        "    mov rax, 1\n"
+        "    ret\n"
+
+        ".global x86_64_read_fault\n"
+        "x86_64_read_fault:\n"
+        "    xor rax, rax\n"
+        "    mov [rdx], rax\n"
+        "    ret\n"
+        :
+        : "i"(&read_region)
+        : "memory"
+    );
+}
+
+extern void x86_64_write_start();
+extern void x86_64_write_end();
+extern void x86_64_write_fault();
+
+static const struct usercopy_region write_region = {
+    .start_ip = x86_64_write_start,
+    .end_ip = x86_64_write_end,
+    .fault_ip = x86_64_write_fault,
+};
+
+[[__naked]]
+bool arch_usercopy_write(__user void* dst, const void* src, size_t len, struct usercopy_region** region) {
+    asm volatile(
+        // Setup regs for `rep movsb`.
+        "    xchg rcx, rdx\n"
+        "    lea rax, [rip + %0]\n"
+        "    mov [rdx], rax\n"
+
+        ".global x86_64_write_start\n"
+        "    x86_64_write_start:\n"
+        "    rep movsb\n"
+
+        ".global x86_64_write_end\n"
+        "    x86_64_write_end:\n"
+        "    xor rax, rax\n"
+        "    xchg [rdx], rax\n"
+        "    mov rax, 1\n"
+        "    ret\n"
+
+        ".global x86_64_write_fault\n"
+        "x86_64_write_fault:\n"
+        "    xor rax, rax\n"
+        "    mov [rdx], rax\n"
+        "    ret\n"
+        :
+        : "i"(&write_region)
+        : "memory"
+    );
+}
+
+extern void x86_64_strlen_start();
+extern void x86_64_strlen_end();
+extern void x86_64_strlen_fault();
+
+static const struct usercopy_region strlen_region = {
+    .start_ip = x86_64_strlen_start,
+    .end_ip = x86_64_strlen_end,
+    .fault_ip = x86_64_strlen_fault,
+};
+
+[[__naked]]
+bool arch_usercopy_strlen(const __user char* str, size_t max, size_t* len, struct usercopy_region** region) {
+    asm volatile(
+        "    lea rax, [rip + %0]\n"
+        "    xchg [rcx], rax\n"
+
+        ".global x86_64_strlen_start\n"
+        "    x86_64_strlen_start:\n"
+        "    xor r8, r8\n"
+        ".Lloop:\n"
+        "    cmp r8, rsi\n"
+        "    je .Lleave\n"
+        "    cmp byte ptr [rdi + r8], 0\n"
+        "    je .Lleave\n"
+        "    inc r8\n"
+        "    jmp .Lloop\n"
+        ".Lleave:\n"
+        "    mov [rdx], r8\n"
+
+        ".global x86_64_strlen_end\n"
+        "x86_64_strlen_end:\n"
+        "    xor rax, rax\n"
+        "    xchg [rcx], rax\n"
+        "    mov rax, 1\n"
+        "    ret\n"
+
+        ".global x86_64_strlen_fault\n"
+        "x86_64_strlen_fault:\n"
+        "    xor rax, rax\n"
+        "    mov [rcx], rax\n"
+        "    ret\n"
+        :
+        : "i"(&strlen_region)
+        : "memory"
+    );
+}

boot/cmdline.c

@@ -1,7 +1,7 @@
-#include <kernel/cmdline.h>
-#include <kernel/init.h>
+#include <zinnia/cmdline.h>
+#include <zinnia/init.h>
+#include <zinnia/stdlib.h>
 #include <stddef.h>
-#include <stdlib.h>
 #include <string.h>
 
 // Defined in linker script.
@@ -9,15 +9,22 @@ extern const struct cmdline_option* __ld_cmdline_start[];
 extern const struct cmdline_option* __ld_cmdline_end[];
 
 static char cmdline_buf[0x1000];
+static char cmdline_raw[0x1000];
 
-[[__init]]
-void cmdline_parse(const char* cmdline) {
-    const size_t len = strnlen(cmdline, sizeof(cmdline_buf) - 1);
+const char* cmdline_get() {
+    return cmdline_raw;
+}
+
+void cmdline_parse_buf(
+    char* cmdline_buf,
+    size_t len,
+    const struct cmdline_option* const* start,
+    const struct cmdline_option* const* end
+) {
     size_t idx = 0;
-    memcpy(cmdline_buf, cmdline, len);
 
     while (1) {
-        const struct cmdline_option** opt = __ld_cmdline_start;
+        const struct cmdline_option* const* opt = start;
         char* name = nullptr;
         char* value = nullptr;
 
@@ -59,9 +66,11 @@ void cmdline_parse(const char* cmdline) {
         }
 
         // Find the corresponding option.
-        while (opt < __ld_cmdline_end) {
+        while (opt < end) {
             const struct cmdline_option* current = *opt;
             if (!strcmp(current->name, name)) {
+                if (value == nullptr)
+                    break;
                 switch (current->option_type) {
                 case CMDLINE_STRING:
                     current->func_str(value);
@@ -100,3 +109,14 @@ void cmdline_parse(const char* cmdline) {
             break;
     }
 }
+
+[[__init]]
+void cmdline_parse(const char* cmdline) {
+    if (cmdline == nullptr)
+        cmdline = "";
+
+    const size_t len = strnlen(cmdline, sizeof(cmdline_buf) - 1);
+    memcpy(cmdline_buf, cmdline, len);
+    memcpy(cmdline_raw, cmdline, len);
+    cmdline_parse_buf(cmdline_buf, len, __ld_cmdline_start, __ld_cmdline_end);
+}

boot/kernel.ld

@@ -1,4 +1,4 @@
-ENTRY(arch_start)
+ENTRY(_start)
 
 PHDRS {
     text    PT_LOAD     FLAGS(5);
@@ -6,6 +6,7 @@ PHDRS {
     data    PT_LOAD     FLAGS(6);
     dynamic PT_DYNAMIC  FLAGS(6);
     percpu  PT_LOAD     FLAGS(6);
+    cmdline 0x60000005;
 }
 
 SECTIONS
@@ -23,18 +24,31 @@ SECTIONS
         __ld_text_end = .;
     } :text
 
-    .rodata ALIGN(CONSTANT(MAXPAGESIZE)) : {
+    .cmdline ALIGN(CONSTANT(MAXPAGESIZE)) : {
         __ld_rodata_start = .;
-
         __ld_cmdline_start = .;
         KEEP(*(.cmdline))
         __ld_cmdline_end = .;
+    } :rodata :cmdline
 
-        __ld_vdso_start = .;
-        KEEP(*(.vdso))
-        __ld_vdso_end = .;
-
+    .rodata : {
         *(.rodata .rodata.*)
+
+        /* Builtin module entry points */
+        . = ALIGN(8);
+        __ld_mod_entry_start = .;
+        KEEP(*(.mod.entry .mod.entry.*))
+        __ld_mod_entry_end = .;
+
+        . = ALIGN(8);
+        __ld_initgraph_nodes_start = .;
+        KEEP(*(.initgraph.nodes))
+        __ld_initgraph_nodes_end = .;
+
+        __ld_initgraph_edges_start = .;
+        KEEP(*(.initgraph.edges))
+        __ld_initgraph_edges_end = .;
+
         *(.got .got.*)
 
         __ld_rodata_end = .;
@@ -43,10 +57,6 @@ SECTIONS
     .data ALIGN(CONSTANT(MAXPAGESIZE)) : {
         __ld_data_start = .;
 
-        __ld_console_start = .;
-        KEEP(*(.console))
-        __ld_console_end = .;
-
         KEEP(*(SORT_BY_NAME(.init.data.*)))
         KEEP(*(.init.data))
         *(.data .data.*)
@@ -54,33 +64,36 @@ SECTIONS
 
     .dynsym : {
         __ld_dynsym_start = .;
-        *(.dynsym)
+        KEEP(*(.dynsym*))
         __ld_dynsym_end = .;
     } :data
 
     .dynstr : {
         __ld_dynstr_start = .;
-        *(.dynstr)
+        KEEP(*(.dynstr*))
         __ld_dynstr_end = .;
     } :data
 
     .dynamic : {
-        *(.dynamic)
+        *(.dynamic*)
     } :data :dynamic
 
-    .bss : {
+    .bss ALIGN(CONSTANT(MAXPAGESIZE)) (NOLOAD) : {
+        *(.*bss .*bss.*)
+        *(COMMON)
+
         /* Small stack to bootstrap the allocator */
+        . = ALIGN(16);
         __ld_stack_bottom = .;
         . += 0x2000;
         __ld_stack_top = .;
-        *(.*bss .*bss.*)
-        *(COMMON)
     } :data
 
     /* Per-CPU data block. MUST always come last. */
     .percpu ALIGN(CONSTANT(MAXPAGESIZE)) : {
         __ld_percpu_start = .;
-        KEEP(*(.percpu))
+        KEEP(*(.percpu.init .percpu.init*))
+        KEEP(*(.percpu.data .percpu.data*))
         . = ALIGN(CONSTANT(MAXPAGESIZE));
         __ld_percpu_end = .;
 

boot/limine/entry.c

@@ -1,15 +1,17 @@
-#include <common/utils.h>
-#include <kernel/alloc.h>
-#include <kernel/cmdline.h>
-#include <kernel/init.h>
-#include <kernel/print.h>
+#include <zinnia/alloc.h>
+#include <zinnia/assert.h>
+#include <zinnia/cmdline.h>
+#include <zinnia/fdt.h>
+#include <zinnia/init.h>
+#include <zinnia/print.h>
+#include <zinnia/utils.h>
 #include <string.h>
 #include "limine.h"
 
 [[__initdata_sorted("limine.0")]]
 static volatile uint64_t limine_start[] = LIMINE_REQUESTS_START_MARKER;
 [[__initdata_sorted("limine.1")]]
-static volatile uint64_t limine_revision[] = LIMINE_BASE_REVISION(4);
+static volatile uint64_t limine_revision[] = LIMINE_BASE_REVISION(6);
 [[__initdata_sorted("limine.2")]]
 static volatile uint64_t limine_end[] = LIMINE_REQUESTS_END_MARKER;
 
@@ -39,14 +41,21 @@ static struct boot_file files[8];
 void kernel_entry() {
     kernel_early_init();
 
-    struct boot_info info;
+    struct boot_info info = {};
 
-    struct limine_memmap_response* mm_res = memmap_request.response;
-    struct limine_module_response* module_res = module_request.response;
-    struct limine_executable_address_response* exec_res = executable_address_request.response;
-    struct limine_executable_file_response* exec_file_res = executable_file_request.response;
+    const struct limine_memmap_response* mm_res = memmap_request.response;
+    const struct limine_hhdm_response* hhdm_res = hhdm_request.response;
+    const struct limine_module_response* module_res = module_request.response;
+    const struct limine_executable_address_response* exec_res = executable_address_request.response;
+    const struct limine_executable_file_response* exec_file_res = executable_file_request.response;
+    const struct limine_rsdp_response* rsdp_res = rsdp_request.response;
+
+    assert(mm_res, "memmap_request returned no response!");
+    assert(hhdm_res, "hhdm_request returned no response!");
 
     info.cmdline = exec_file_res->executable_file->string;
+    info.kernel_file.data = (phys_t)((uintptr_t)exec_file_res->executable_file->address - hhdm_res->offset);
+    info.kernel_file.length = exec_file_res->executable_file->size;
 
     info.num_mem_maps = MIN(ARRAY_SIZE(mem), mm_res->entry_count);
     for (size_t i = 0; i < info.num_mem_maps; i++) {
@@ -74,20 +83,53 @@ void kernel_entry() {
         info.files = files;
         info.num_files = MIN(ARRAY_SIZE(files), module_res->module_count);
         for (size_t i = 0; i < info.num_files; i++) {
-            files[i].data = (phys_t)module_res->modules[i]->address - hhdm_request.response->offset;
+            files[i].data = (phys_t)module_res->modules[i]->address - hhdm_res->offset;
             files[i].length = module_res->modules[i]->size;
-            strncpy(files[i].path, module_res->modules[i]->path, sizeof(files[i].path));
+            strncpy(files[i].path, module_res->modules[i]->path, sizeof(files[i].path) - 1);
+            files[i].path[sizeof(files[i].path) - 1] = 0;
         }
     }
 
     info.mem_map = mem;
     info.phys_base = (phys_t)exec_res->physical_base;
     info.virt_base = (uintptr_t)exec_res->virtual_base;
-    info.hhdm_base = (uintptr_t)hhdm_request.response->offset;
+    info.hhdm_base = (uintptr_t)hhdm_res->offset;
 
-    info.rsdp = (phys_t)rsdp_request.response->address - info.hhdm_base;
+    const struct limine_dtb_response* dtb_res = dtb_request.response;
+    if (dtb_res && dtb_res->dtb_ptr) {
+        info.dtb = (phys_t)((uintptr_t)dtb_res->dtb_ptr - hhdm_res->offset);
+        info.dtb_size = fdt_read_u32((const uint8_t*)dtb_res->dtb_ptr + 4);
+    }
+
+    const struct limine_framebuffer_response* fb_res = framebuffer_request.response;
+    if (fb_res) {
+        // Only use the first framebuffer.
+        if (fb_res->framebuffer_count >= 1) {
+            const struct limine_framebuffer* fb = framebuffer_request.response->framebuffers[0];
+            info.fb.base = (phys_t)((uintptr_t)fb->address - hhdm_res->offset);
+            info.fb.width = fb->width;
+            info.fb.height = fb->height;
+            info.fb.pitch = fb->pitch;
+            info.fb.bytes_per_pixel = fb->bpp / 8;
+
+            info.fb.red.shift = fb->red_mask_shift;
+            info.fb.red.size = fb->red_mask_size;
+
+            info.fb.green.shift = fb->green_mask_shift;
+            info.fb.green.size = fb->green_mask_size;
+
+            info.fb.blue.shift = fb->blue_mask_shift;
+            info.fb.blue.size = fb->blue_mask_size;
+        }
+    }
+
+#if CONFIG_ACPI
+    if (rsdp_request.response) {
+        info.rsdp = (phys_t)rsdp_request.response->address;
+        if (info.rsdp >= info.hhdm_base)
+            info.rsdp -= info.hhdm_base;
+    }
+#endif
 
     kernel_main(&info);
 }
-
-phys_t rsdp_addr;

boot/limine/limine.h

@@ -0,0 +1,669 @@
+/* SPDX-License-Identifier: 0BSD */
+
+/* Copyright (C) 2022-2026 Mintsuki and contributors.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef LIMINE_H
+#define LIMINE_H 1
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Misc */
+
+#ifdef LIMINE_NO_POINTERS
+#  define LIMINE_PTR(TYPE) uint64_t
+#else
+#  define LIMINE_PTR(TYPE) TYPE
+#endif
+
+#define LIMINE_REQUESTS_START_MARKER { 0xf6b8f4b39de7d1ae, 0xfab91a6940fcb9cf, \
+                                       0x785c6ed015d3e316, 0x181e920a7852b9d9 }
+#define LIMINE_REQUESTS_END_MARKER { 0xadc0e0531bb10d03, 0x9572709f31764c62 }
+
+#define LIMINE_BASE_REVISION(N) { 0xf9562b2d5c95a6c8, 0x6a7b384944536bdc, (N) }
+
+#define LIMINE_BASE_REVISION_SUPPORTED(VAR) ((VAR)[2] == 0)
+
+#define LIMINE_LOADED_BASE_REVISION_VALID(VAR) ((VAR)[1] != 0x6a7b384944536bdc)
+#define LIMINE_LOADED_BASE_REVISION(VAR) ((VAR)[1])
+
+#define LIMINE_COMMON_MAGIC 0xc7b1dd30df4c8b88, 0x0a82e883a194f07b
+
+struct limine_uuid {
+    uint32_t a;
+    uint16_t b;
+    uint16_t c;
+    uint8_t d[8];
+};
+
+#define LIMINE_MEDIA_TYPE_GENERIC 0
+#define LIMINE_MEDIA_TYPE_OPTICAL 1
+#define LIMINE_MEDIA_TYPE_TFTP 2
+
+struct limine_file {
+    uint64_t revision;
+    LIMINE_PTR(void *) address;
+    uint64_t size;
+    LIMINE_PTR(char *) path;
+    LIMINE_PTR(char *) string;
+    uint32_t media_type;
+    uint32_t unused;
+    uint8_t tftp_ipv4[4];
+    uint32_t tftp_port;
+    uint32_t partition_index;
+    uint32_t mbr_disk_id;
+    struct limine_uuid gpt_disk_uuid;
+    struct limine_uuid gpt_part_uuid;
+    struct limine_uuid part_uuid;
+};
+
+/* Boot info */
+
+#define LIMINE_BOOTLOADER_INFO_REQUEST_ID { LIMINE_COMMON_MAGIC, 0xf55038d8e2a1202f, 0x279426fcf5f59740 }
+
+struct limine_bootloader_info_response {
+    uint64_t revision;
+    LIMINE_PTR(char *) name;
+    LIMINE_PTR(char *) version;
+};
+
+struct limine_bootloader_info_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_bootloader_info_response *) response;
+};
+
+/* Executable command line */
+
+#define LIMINE_EXECUTABLE_CMDLINE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x4b161536e598651e, 0xb390ad4a2f1f303a }
+
+struct limine_executable_cmdline_response {
+    uint64_t revision;
+    LIMINE_PTR(char *) cmdline;
+};
+
+struct limine_executable_cmdline_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_executable_cmdline_response *) response;
+};
+
+/* Firmware type */
+
+#define LIMINE_FIRMWARE_TYPE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x8c2f75d90bef28a8, 0x7045a4688eac00c3 }
+
+#define LIMINE_FIRMWARE_TYPE_X86BIOS 0
+#define LIMINE_FIRMWARE_TYPE_EFI32 1
+#define LIMINE_FIRMWARE_TYPE_EFI64 2
+#define LIMINE_FIRMWARE_TYPE_SBI 3
+
+struct limine_firmware_type_response {
+    uint64_t revision;
+    uint64_t firmware_type;
+};
+
+struct limine_firmware_type_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_firmware_type_response *) response;
+};
+
+/* Stack size */
+
+#define LIMINE_STACK_SIZE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x224ef0460a8e8926, 0xe1cb0fc25f46ea3d }
+
+struct limine_stack_size_response {
+    uint64_t revision;
+};
+
+struct limine_stack_size_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_stack_size_response *) response;
+    uint64_t stack_size;
+};
+
+/* HHDM */
+
+#define LIMINE_HHDM_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x48dcf1cb8ad2b852, 0x63984e959a98244b }
+
+struct limine_hhdm_response {
+    uint64_t revision;
+    uint64_t offset;
+};
+
+struct limine_hhdm_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_hhdm_response *) response;
+};
+
+/* Framebuffer */
+
+#define LIMINE_FRAMEBUFFER_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x9d5827dcd881dd75, 0xa3148604f6fab11b }
+
+#define LIMINE_FRAMEBUFFER_RGB 1
+
+struct limine_video_mode {
+    uint64_t pitch;
+    uint64_t width;
+    uint64_t height;
+    uint16_t bpp;
+    uint8_t memory_model;
+    uint8_t red_mask_size;
+    uint8_t red_mask_shift;
+    uint8_t green_mask_size;
+    uint8_t green_mask_shift;
+    uint8_t blue_mask_size;
+    uint8_t blue_mask_shift;
+};
+
+struct limine_framebuffer {
+    LIMINE_PTR(void *) address;
+    uint64_t width;
+    uint64_t height;
+    uint64_t pitch;
+    uint16_t bpp;
+    uint8_t memory_model;
+    uint8_t red_mask_size;
+    uint8_t red_mask_shift;
+    uint8_t green_mask_size;
+    uint8_t green_mask_shift;
+    uint8_t blue_mask_size;
+    uint8_t blue_mask_shift;
+    uint8_t unused[7];
+    uint64_t edid_size;
+    LIMINE_PTR(void *) edid;
+    /* Response revision 1 */
+    uint64_t mode_count;
+    LIMINE_PTR(struct limine_video_mode **) modes;
+};
+
+struct limine_framebuffer_response {
+    uint64_t revision;
+    uint64_t framebuffer_count;
+    LIMINE_PTR(struct limine_framebuffer **) framebuffers;
+};
+
+struct limine_framebuffer_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_framebuffer_response *) response;
+};
+
+/* Flanterm FB init params */
+
+#define LIMINE_FLANTERM_FB_INIT_PARAMS_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x3259399fe7c5f126, 0xe01c1c8c5db9d1a9 }
+
+#define LIMINE_FLANTERM_FB_ROTATE_0 0
+#define LIMINE_FLANTERM_FB_ROTATE_90 1
+#define LIMINE_FLANTERM_FB_ROTATE_180 2
+#define LIMINE_FLANTERM_FB_ROTATE_270 3
+
+struct limine_flanterm_fb_init_params {
+    LIMINE_PTR(uint32_t *) canvas;
+    uint64_t canvas_size;
+    uint32_t ansi_colours[8];
+    uint32_t ansi_bright_colours[8];
+    uint32_t default_bg;
+    uint32_t default_fg;
+    uint32_t default_bg_bright;
+    uint32_t default_fg_bright;
+    LIMINE_PTR(void *) font;
+    uint64_t font_width;
+    uint64_t font_height;
+    uint64_t font_spacing;
+    uint64_t font_scale_x;
+    uint64_t font_scale_y;
+    uint64_t margin;
+    uint64_t rotation;
+};
+
+struct limine_flanterm_fb_init_params_response {
+    uint64_t revision;
+    uint64_t entry_count;
+    LIMINE_PTR(struct limine_flanterm_fb_init_params **) entries;
+};
+
+struct limine_flanterm_fb_init_params_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_flanterm_fb_init_params_response *) response;
+};
+
+/* Paging mode */
+
+#define LIMINE_PAGING_MODE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x95c1a0edab0944cb, 0xa4e5cb3842f7488a }
+
+#define LIMINE_PAGING_MODE_X86_64_4LVL 0
+#define LIMINE_PAGING_MODE_X86_64_5LVL 1
+#define LIMINE_PAGING_MODE_X86_64_MIN LIMINE_PAGING_MODE_X86_64_4LVL
+#define LIMINE_PAGING_MODE_X86_64_DEFAULT LIMINE_PAGING_MODE_X86_64_4LVL
+
+#define LIMINE_PAGING_MODE_AARCH64_4LVL 0
+#define LIMINE_PAGING_MODE_AARCH64_5LVL 1
+#define LIMINE_PAGING_MODE_AARCH64_MIN LIMINE_PAGING_MODE_AARCH64_4LVL
+#define LIMINE_PAGING_MODE_AARCH64_DEFAULT LIMINE_PAGING_MODE_AARCH64_4LVL
+
+#define LIMINE_PAGING_MODE_RISCV_SV39 0
+#define LIMINE_PAGING_MODE_RISCV_SV48 1
+#define LIMINE_PAGING_MODE_RISCV_SV57 2
+#define LIMINE_PAGING_MODE_RISCV_MIN LIMINE_PAGING_MODE_RISCV_SV39
+#define LIMINE_PAGING_MODE_RISCV_DEFAULT LIMINE_PAGING_MODE_RISCV_SV48
+
+#define LIMINE_PAGING_MODE_LOONGARCH_4LVL 0
+#define LIMINE_PAGING_MODE_LOONGARCH_MIN LIMINE_PAGING_MODE_LOONGARCH_4LVL
+#define LIMINE_PAGING_MODE_LOONGARCH_DEFAULT LIMINE_PAGING_MODE_LOONGARCH_4LVL
+
+struct limine_paging_mode_response {
+    uint64_t revision;
+    uint64_t mode;
+};
+
+struct limine_paging_mode_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_paging_mode_response *) response;
+    uint64_t mode;
+    uint64_t max_mode;
+    uint64_t min_mode;
+};
+
+/* MP */
+
+#define LIMINE_MP_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x95a67b819a1b857e, 0xa0b61b723b6a73e0 }
+
+struct limine_mp_info;
+
+typedef void (*limine_goto_address)(struct limine_mp_info *);
+
+#if defined (__x86_64__) || defined (__i386__)
+
+#define LIMINE_MP_RESPONSE_X86_64_X2APIC (1 << 0)
+
+struct limine_mp_info {
+    uint32_t processor_id;
+    uint32_t lapic_id;
+    uint64_t reserved;
+    LIMINE_PTR(limine_goto_address) goto_address;
+    uint64_t extra_argument;
+};
+
+struct limine_mp_response {
+    uint64_t revision;
+    uint32_t flags;
+    uint32_t bsp_lapic_id;
+    uint64_t cpu_count;
+    LIMINE_PTR(struct limine_mp_info **) cpus;
+};
+
+#elif defined (__aarch64__)
+
+struct limine_mp_info {
+    uint32_t processor_id;
+    uint32_t reserved1;
+    uint64_t mpidr;
+    uint64_t reserved;
+    LIMINE_PTR(limine_goto_address) goto_address;
+    uint64_t extra_argument;
+};
+
+struct limine_mp_response {
+    uint64_t revision;
+    uint64_t flags;
+    uint64_t bsp_mpidr;
+    uint64_t cpu_count;
+    LIMINE_PTR(struct limine_mp_info **) cpus;
+};
+
+#elif defined (__riscv) && (__riscv_xlen == 64)
+
+struct limine_mp_info {
+    uint64_t processor_id;
+    uint64_t hartid;
+    uint64_t reserved;
+    LIMINE_PTR(limine_goto_address) goto_address;
+    uint64_t extra_argument;
+};
+
+struct limine_mp_response {
+    uint64_t revision;
+    uint64_t flags;
+    uint64_t bsp_hartid;
+    uint64_t cpu_count;
+    LIMINE_PTR(struct limine_mp_info **) cpus;
+};
+
+#elif defined (__loongarch__) && (__loongarch_grlen == 64)
+
+struct limine_mp_info {
+    uint64_t processor_id;
+    uint64_t phys_id;
+    uint64_t reserved;
+    LIMINE_PTR(limine_goto_address) goto_address;
+    uint64_t extra_argument;
+};
+
+struct limine_mp_response {
+    uint64_t revision;
+    uint64_t flags;
+    uint64_t bsp_phys_id;
+    uint64_t cpu_count;
+    LIMINE_PTR(struct limine_mp_info **) cpus;
+};
+
+#else
+#error Unknown architecture
+#endif
+
+#define LIMINE_MP_REQUEST_X86_64_X2APIC (1 << 0)
+
+struct limine_mp_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_mp_response *) response;
+    uint64_t flags;
+};
+
+/* Memory map */
+
+#define LIMINE_MEMMAP_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x67cf3d9d378a806f, 0xe304acdfc50c3c62 }
+
+#define LIMINE_MEMMAP_USABLE                 0
+#define LIMINE_MEMMAP_RESERVED               1
+#define LIMINE_MEMMAP_ACPI_RECLAIMABLE       2
+#define LIMINE_MEMMAP_ACPI_NVS               3
+#define LIMINE_MEMMAP_BAD_MEMORY             4
+#define LIMINE_MEMMAP_BOOTLOADER_RECLAIMABLE 5
+#define LIMINE_MEMMAP_EXECUTABLE_AND_MODULES 6
+#define LIMINE_MEMMAP_FRAMEBUFFER            7
+#define LIMINE_MEMMAP_RESERVED_MAPPED        8
+
+struct limine_memmap_entry {
+    uint64_t base;
+    uint64_t length;
+    uint64_t type;
+};
+
+struct limine_memmap_response {
+    uint64_t revision;
+    uint64_t entry_count;
+    LIMINE_PTR(struct limine_memmap_entry **) entries;
+};
+
+struct limine_memmap_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_memmap_response *) response;
+};
+
+/* Entry point */
+
+#define LIMINE_ENTRY_POINT_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x13d86c035a1cd3e1, 0x2b0caa89d8f3026a }
+
+typedef void (*limine_entry_point)(void);
+
+struct limine_entry_point_response {
+    uint64_t revision;
+};
+
+struct limine_entry_point_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_entry_point_response *) response;
+    LIMINE_PTR(limine_entry_point) entry;
+};
+
+/* Executable File */
+
+#define LIMINE_EXECUTABLE_FILE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0xad97e90e83f1ed67, 0x31eb5d1c5ff23b69 }
+
+struct limine_executable_file_response {
+    uint64_t revision;
+    LIMINE_PTR(struct limine_file *) executable_file;
+};
+
+struct limine_executable_file_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_executable_file_response *) response;
+};
+
+/* Module */
+
+#define LIMINE_MODULE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x3e7e279702be32af, 0xca1c4f3bd1280cee }
+
+#define LIMINE_INTERNAL_MODULE_REQUIRED (1 << 0)
+#define LIMINE_INTERNAL_MODULE_COMPRESSED (1 << 1)
+
+struct limine_internal_module {
+    LIMINE_PTR(const char *) path;
+    LIMINE_PTR(const char *) string;
+    uint64_t flags;
+};
+
+struct limine_module_response {
+    uint64_t revision;
+    uint64_t module_count;
+    LIMINE_PTR(struct limine_file **) modules;
+};
+
+struct limine_module_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_module_response *) response;
+
+    /* Request revision 1 */
+    uint64_t internal_module_count;
+    LIMINE_PTR(struct limine_internal_module **) internal_modules;
+};
+
+/* RSDP */
+
+#define LIMINE_RSDP_REQUEST_ID { LIMINE_COMMON_MAGIC, 0xc5e77b6b397e7b43, 0x27637845accdcf3c }
+
+struct limine_rsdp_response {
+    uint64_t revision;
+    LIMINE_PTR(void *) address;
+};
+
+struct limine_rsdp_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_rsdp_response *) response;
+};
+
+/* SMBIOS */
+
+#define LIMINE_SMBIOS_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x9e9046f11e095391, 0xaa4a520fefbde5ee }
+
+struct limine_smbios_response {
+    uint64_t revision;
+    LIMINE_PTR(void *) entry_32;
+    LIMINE_PTR(void *) entry_64;
+};
+
+struct limine_smbios_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_smbios_response *) response;
+};
+
+/* EFI system table */
+
+#define LIMINE_EFI_SYSTEM_TABLE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x5ceba5163eaaf6d6, 0x0a6981610cf65fcc }
+
+struct limine_efi_system_table_response {
+    uint64_t revision;
+    LIMINE_PTR(void *) address;
+};
+
+struct limine_efi_system_table_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_efi_system_table_response *) response;
+};
+
+/* TPM event log */
+
+#define LIMINE_TPM_EVENT_LOG_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x98e094fc7e76e979, 0xee8d8775c54e1d1f }
+
+#define LIMINE_TPM_EVENT_LOG_FORMAT_TCG_1_2 1
+#define LIMINE_TPM_EVENT_LOG_FORMAT_TCG_2   2
+
+struct limine_tpm_event_log_response {
+    uint64_t revision;
+    uint64_t format;
+    uint64_t size;
+    LIMINE_PTR(void *) address;
+};
+
+struct limine_tpm_event_log_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_tpm_event_log_response *) response;
+};
+
+/* EFI memory map */
+
+#define LIMINE_EFI_MEMMAP_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x7df62a431d6872d5, 0xa4fcdfb3e57306c8 }
+
+struct limine_efi_memmap_response {
+    uint64_t revision;
+    LIMINE_PTR(void *) memmap;
+    uint64_t memmap_size;
+    uint64_t desc_size;
+    uint64_t desc_version;
+};
+
+struct limine_efi_memmap_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_efi_memmap_response *) response;
+};
+
+/* Date at boot */
+
+#define LIMINE_DATE_AT_BOOT_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x502746e184c088aa, 0xfbc5ec83e6327893 }
+
+struct limine_date_at_boot_response {
+    uint64_t revision;
+    int64_t timestamp;
+};
+
+struct limine_date_at_boot_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_date_at_boot_response *) response;
+};
+
+/* Executable address */
+
+#define LIMINE_EXECUTABLE_ADDRESS_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x71ba76863cc55f63, 0xb2644a48c516a487 }
+
+struct limine_executable_address_response {
+    uint64_t revision;
+    uint64_t physical_base;
+    uint64_t virtual_base;
+};
+
+struct limine_executable_address_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_executable_address_response *) response;
+};
+
+/* Device Tree Blob */
+
+#define LIMINE_DTB_REQUEST_ID { LIMINE_COMMON_MAGIC, 0xb40ddb48fb54bac7, 0x545081493f81ffb7 }
+
+struct limine_dtb_response {
+    uint64_t revision;
+    LIMINE_PTR(void *) dtb_ptr;
+};
+
+struct limine_dtb_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_dtb_response *) response;
+};
+
+/* RISC-V Boot Hart ID */
+
+#define LIMINE_RISCV_BSP_HARTID_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x1369359f025525f9, 0x2ff2a56178391bb6 }
+
+struct limine_riscv_bsp_hartid_response {
+    uint64_t revision;
+    uint64_t bsp_hartid;
+};
+
+struct limine_riscv_bsp_hartid_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_riscv_bsp_hartid_response *) response;
+};
+
+/* Bootloader Performance */
+
+#define LIMINE_BOOTLOADER_PERFORMANCE_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x6b50ad9bf36d13ad, 0xdc4c7e88fc759e17 }
+
+struct limine_bootloader_performance_response {
+    uint64_t revision;
+    uint64_t reset_usec;
+    uint64_t init_usec;
+    uint64_t exec_usec;
+};
+
+struct limine_bootloader_performance_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_bootloader_performance_response *) response;
+};
+
+#define LIMINE_X86_64_KEEP_IOMMU_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x8ebaabe51f490179, 0x2aa86a59ffb4ab0f }
+
+struct limine_x86_64_keep_iommu_response {
+    uint64_t revision;
+};
+
+struct limine_x86_64_keep_iommu_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_x86_64_keep_iommu_response *) response;
+};
+
+/* TSC (Timestamp Counter) Frequency */
+
+#define LIMINE_TSC_FREQUENCY_REQUEST_ID { LIMINE_COMMON_MAGIC, 0x10f2ee1d87d195e4, 0xf747a2b78f6ddb31 }
+
+struct limine_tsc_frequency_response {
+    uint64_t revision;
+    uint64_t frequency;
+};
+
+struct limine_tsc_frequency_request {
+    uint64_t id[4];
+    uint64_t revision;
+    LIMINE_PTR(struct limine_tsc_frequency_response *) response;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

boot/main.c

@@ -0,0 +1,97 @@
+#include <zinnia/alloc.h>
+#include <zinnia/assert.h>
+#include <zinnia/clock.h>
+#include <zinnia/cmdline.h>
+#include <zinnia/compiler.h>
+#include <zinnia/console.h>
+#include <zinnia/elf.h>
+#include <zinnia/init.h>
+#include <zinnia/initgraph.h>
+#include <zinnia/irq.h>
+#include <zinnia/module.h>
+#include <zinnia/percpu.h>
+#include <zinnia/print.h>
+#include <zinnia/sched.h>
+#include <zinnia/utils.h>
+#include <zinnia/vma.h>
+#include <zinnia/vmo.h>
+#include <config.h>
+#include <stdint.h>
+
+static const char zinnia_banner[] = "Zinnia " ZINNIA_VERSION " " CONFIG_KERNEL_FLAVOR " (" ZINNIA_ARCH
+                                    ", " ZINNIA_COMPILER_ID ", " ZINNIA_LINKER_ID ")";
+
+static void kernel_main_task(uintptr_t arg0) {
+    errno_t status = 0;
+    struct boot_info* info = (struct boot_info*)arg0;
+
+    log("main: Hello from main task!\n");
+
+    // Finish the initgraph.
+    initgraph_run(nullptr, info);
+
+    module_init();
+
+    // TODO: Try to run init.
+
+    assert(info->num_files >= 1, "No init executable provided");
+
+    struct vma* init_space;
+    assert(vma_new(&init_space) == 0, "");
+
+    struct boot_file* file_data = &info->files[0];
+    struct task* init_task = nullptr;
+
+    struct paged_vmo* init_file;
+    status = vmo_new_phys(&init_file);
+    assert(status == 0, "Failed to allocate a memory object");
+
+    vmo_write(&init_file->object, 0, HHDM_PTR(file_data->data), file_data->length, nullptr);
+
+    // Load init.
+    const char* init_argv[] = {"init", nullptr};
+    const char* init_envp[] = {nullptr};
+
+    struct exec_info exec = {
+        .space = init_space,
+        .file_obj = &init_file->object,
+        .argv = init_argv,
+        .envp = init_envp,
+    };
+
+    status = elf_load(&exec, &init_task);
+    vmo_unref(&init_file->object);
+
+    assert(status == 0, "Failed to load init process (%i)", status);
+    sched_add_task(&percpu_get()->sched, init_task);
+
+    while (true) {
+        irq_wait();
+    }
+}
+
+[[__init]]
+void kernel_early_init() {
+    percpu_bsp_init();
+    percpu_get()->online = true;
+    irq_lock();
+}
+
+[[noreturn]]
+void kernel_main(struct boot_info* info) {
+    cmdline_parse(info->cmdline);
+
+    log("%s\n", zinnia_banner); // Say hello!
+    log("Command line: %s\n", info->cmdline);
+
+    initgraph_run(sched_stage, info);
+
+    struct task* main_task;
+    task_create("main", &kernel_vma, kernel_main_task, (uintptr_t)info, &main_task);
+    sched_add_task(&percpu_get()->sched, main_task);
+
+    irq_unlock();
+    sched_yield(&percpu_get()->sched);
+
+    unreachable();
+}

dev/Kconfig

@@ -0,0 +1,19 @@
+menu "Device Drivers"
+
+config OF
+  bool "Support for OpenFirmware"
+  default y
+  help
+    Adds support for flattened device trees and OF platform drivers.
+
+config ACPI
+  bool "Support for ACPI firmware"
+  default y
+  help
+    Adds support for ACPI firmware, tables and devices.
+
+source "dev/block/Kconfig"
+source "dev/pci/Kconfig"
+source "dev/video/Kconfig"
+
+endmenu

dev/acpi/include/zinnia/acpi.h

@@ -0,0 +1,17 @@
+#pragma once
+
+#include <zinnia/init.h>
+#include <zinnia/initgraph.h>
+#include <zinnia/types.h>
+#include <stdint.h>
+
+INIT_EXTERN(acpi_stage);
+
+extern phys_t acpi_rsdp_addr;
+
+struct acpi_match {
+    const char* hid;
+    uintptr_t data;
+};
+
+#define ACPI_MATCH_HID(id) .hid = (id)

dev/acpi/init.c

@@ -0,0 +1,45 @@
+#define pr_fmt(fmt) "acpi: " fmt
+
+#include <zinnia/acpi.h>
+#include <zinnia/alloc.h>
+#include <zinnia/cmdline.h>
+#include <zinnia/percpu.h>
+#include <zinnia/print.h>
+#include <zinnia/types.h>
+#include <uacpi/status.h>
+#include <uacpi/tables.h>
+#include <uacpi/uacpi.h>
+
+phys_t acpi_rsdp_addr = 0;
+
+static char table_buf[0x1000];
+
+static bool use_acpi = true;
+void use_acpi_option(bool use) {
+    use_acpi = use;
+}
+CMDLINE_OPTION("acpi", "Enable ACPI firmware subsystem", use_acpi_option);
+
+[[__init]]
+static bool acpi_stage_init(struct boot_info* info) {
+    if (!use_acpi) {
+        log_warn("ACPI disabled on the command line!\n");
+        return false;
+    }
+
+    if (!info->rsdp) {
+        log_warn("No RSDP was passed, unable to start ACPI subsystem!\n");
+        return false;
+    }
+    acpi_rsdp_addr = info->rsdp;
+
+    if (uacpi_setup_early_table_access(table_buf, sizeof(table_buf)) != UACPI_STATUS_OK) {
+        log_err("Failed to set up early table access!\n");
+        return false;
+    }
+
+    return true;
+}
+INIT_TASK(acpi_stage, "dev.acpi", acpi_stage_init);
+INIT_DEPENDS(acpi_stage, mem_stage);
+INIT_ENTAILS(acpi_stage, percpu_stage);

dev/acpi/mcfg.c

@@ -0,0 +1,32 @@
+#define pr_fmt(fmt) "acpi: " fmt
+
+#include <zinnia/acpi.h>
+#include <zinnia/pci.h>
+#include <zinnia/print.h>
+#include <uacpi/acpi.h>
+#include <uacpi/status.h>
+#include <uacpi/tables.h>
+
+[[__init]]
+static void acpi_mcfg_stage_init(struct boot_info*) {
+    uacpi_table table = {};
+    if (uacpi_table_find_by_signature(ACPI_MCFG_SIGNATURE, &table) != UACPI_STATUS_OK)
+        return;
+
+    struct acpi_mcfg* mcfg = table.ptr;
+    size_t count = 0;
+    if (mcfg->hdr.length > sizeof(*mcfg))
+        count = (mcfg->hdr.length - sizeof(*mcfg)) / sizeof(struct acpi_mcfg_allocation);
+
+    for (size_t i = 0; i < count; i++) {
+        struct acpi_mcfg_allocation* entry = &mcfg->entries[i];
+        errno_t status = pci_ecam_register(entry->address, entry->segment, entry->start_bus, entry->end_bus);
+        if (status != 0)
+            log_warn("Failed to register ECAM for segment %hu: %i\n", entry->segment, status);
+    }
+
+    uacpi_table_unref(&table);
+}
+INIT_TASK(acpi_mcfg_stage, "dev.acpi.mcfg", acpi_mcfg_stage_init);
+INIT_DEPENDS(acpi_mcfg_stage, acpi_stage);
+INIT_ENTAILS(acpi_mcfg_stage, pci_stage);

dev/acpi/meson.build

@@ -0,0 +1,20 @@
+uacpi = subproject('uacpi')
+
+kernel_sources += uacpi.get_variable('sources')
+kernel_sources += files(
+    'init.c',
+    'uacpi_glue.c',
+)
+
+if kconfig.get('CONFIG_PCI', 'n') == 'y'
+    kernel_sources += files('mcfg.c')
+endif
+
+kernel_includes += uacpi.get_variable('includes')
+kernel_includes += include_directories('include')
+
+kernel_c_args += [
+    '-DUACPI_FORMATTED_LOGGING',
+    '-DUACPI_BAREBONES_MODE', # TODO: Remove
+    '-DUACPI_OVERRIDE_TYPES',
+]

dev/acpi/uacpi_glue.c

@@ -0,0 +1,73 @@
+#include <zinnia/acpi.h>
+#include <zinnia/alloc.h>
+#include <zinnia/console.h>
+#include <zinnia/init.h>
+#include <zinnia/mmio.h>
+#include <zinnia/pmap.h>
+#include <zinnia/print.h>
+#include <zinnia/utils.h>
+#include <zinnia/virt.h>
+#include <zinnia/vma.h>
+#include <arch/mem.h>
+#include <stdarg.h>
+#include <uacpi/kernel_api.h>
+#include <uacpi/status.h>
+#include <uacpi/types.h>
+
+uacpi_status uacpi_kernel_get_rsdp(uacpi_phys_addr* out_rsdp_address) {
+    *out_rsdp_address = (uacpi_phys_addr)acpi_rsdp_addr;
+    return UACPI_STATUS_OK;
+}
+
+void* uacpi_kernel_map(uacpi_phys_addr addr, uacpi_size len) {
+    uintptr_t aligned_addr = ALIGN_DOWN(addr, arch_mem_page_size());
+    uintptr_t difference = addr - aligned_addr;
+    size_t aligned_len = ALIGN_UP(len + difference, arch_mem_page_size());
+
+    uintptr_t vaddr = vm_alloc(aligned_len);
+    if (!vaddr)
+        return nullptr;
+
+    for (size_t i = 0; i < aligned_len; i += arch_mem_page_size()) {
+        pmap_map(&kernel_vma.pmap, vaddr + i, aligned_addr + i, PTE_READ | PTE_WRITE, CACHE_ANY);
+    }
+
+    return (void*)(vaddr + difference);
+}
+
+void uacpi_kernel_unmap(void* addr, uacpi_size len) {
+    uintptr_t aligned_addr = ALIGN_DOWN((uintptr_t)addr, arch_mem_page_size());
+    uintptr_t difference = (uintptr_t)addr - aligned_addr;
+    size_t aligned_len = ALIGN_UP(len + difference, arch_mem_page_size());
+
+    for (size_t i = 0; i < aligned_len; i += arch_mem_page_size())
+        pmap_unmap(&kernel_vma.pmap, aligned_addr + i);
+    vm_free(aligned_addr, aligned_len);
+}
+
+static enum log_level acpi_log_level(uacpi_log_level lvl) {
+    switch (lvl) {
+    case UACPI_LOG_ERROR:
+        return LOG_ERR;
+
+    case UACPI_LOG_WARN:
+        return LOG_WARN;
+
+    case UACPI_LOG_INFO:
+        return LOG_INFO;
+
+    default:
+        return LOG_DEBUG;
+    }
+}
+
+void uacpi_kernel_log(uacpi_log_level lvl, const uacpi_char* msg, ...) {
+    va_list args;
+    va_start(args, msg);
+    log_vwrite_prefixed(acpi_log_level(lvl), "acpi: ", msg, args);
+    va_end(args);
+}
+
+void uacpi_kernel_vlog(uacpi_log_level lvl, const uacpi_char* msg, uacpi_va_list args) {
+    log_vwrite_prefixed(acpi_log_level(lvl), "acpi: ", msg, args);
+}

dev/block/Kconfig

@@ -0,0 +1,5 @@
+menu "Block device drivers"
+
+source "dev/block/nvme/Kconfig"
+
+endmenu

dev/block/meson.build

@@ -0,0 +1,3 @@
+if kconfig.get('CONFIG_NVME_CORE', 'n') != 'n'
+    subdir('nvme')
+endif

dev/block/nvme/Kconfig

@@ -0,0 +1,13 @@
+menu "NVMe Support"
+
+config NVME_CORE
+  bool
+  default y
+
+config NVME_PCI
+  bool "NVMe via PCI transport"
+  default y
+  depends on PCI
+  depends on NVME_CORE
+
+endmenu

dev/block/nvme/core.c

@@ -0,0 +1,41 @@
+#define pr_fmt(fmt) "nvme: " fmt
+
+#include <zinnia/fdt.h>
+#include <zinnia/module.h>
+#include <zinnia/pci.h>
+#include <zinnia/print.h>
+#include <zinnia/utils.h>
+#include <config.h>
+
+#if CONFIG_NVME_PCI
+#include "nvme_pci.h"
+#endif
+
+struct nvme_dev {
+#if CONFIG_NVME_PCI
+    struct pci_device pci_dev;
+#endif
+};
+
+errno_t nvme_init(struct module* mod) {
+    errno_t status = 0;
+
+#if CONFIG_NVME_PCI
+    status = pci_driver_register(&nvme_driver);
+#endif
+
+    return status;
+}
+
+errno_t nvme_exit(struct module* mod) {
+    // TODO: Unregister
+    return 0;
+}
+
+MODULE_ENTRY(nvme_init);
+MODULE_EXIT(nvme_exit);
+
+MODULE_DESC("NVMe Block Devices");
+MODULE_AUTHOR("Marvin Friedrich");
+MODULE_LICENSE("ISC");
+MODULE_VERSION("1.0");

dev/block/nvme/meson.build

@@ -0,0 +1,12 @@
+nvme_sources = files('core.c')
+
+if kconfig.get('CONFIG_NVME_PCI', 'n') == 'y'
+    nvme_sources += files('pci.c')
+endif
+
+modules += {
+    'nvme': {
+        'modular': kconfig.get('CONFIG_NVME_CORE') == 'm',
+        'sources': nvme_sources,
+    },
+}

dev/block/nvme/nvme_pci.h

@@ -0,0 +1,3 @@
+#pragma once
+
+extern struct pci_driver nvme_driver;

dev/block/nvme/pci.c

@@ -0,0 +1,23 @@
+#include <zinnia/errno.h>
+#include <zinnia/module.h>
+#include <zinnia/pci.h>
+
+static errno_t nvme_pci_probe(struct pci_device* dev, const struct pci_match* match) {
+    pci_log(dev, "Detected controller \n");
+
+    return 0;
+}
+
+static const struct pci_match nvme_match[] = {
+    // Generic NVMe device. Assume no quirks or any funny business.
+    {PCI_MATCH_CLASS(1, 8, 2), .data = 0},
+};
+
+MATCH_TABLE("pci", nvme_match);
+
+struct pci_driver nvme_driver = {
+    .name = "nvme_pci",
+    .match = nvme_match,
+    .num_matches = ARRAY_SIZE(nvme_match),
+    .probe = nvme_pci_probe,
+};

dev/block/nvme/spec.h

@@ -0,0 +1 @@
+#pragma once

dev/common/memfiles.c

@@ -0,0 +1 @@
+

dev/common/meson.build

@@ -0,0 +1,3 @@
+kernel_sources += files(
+    'memfiles.c',
+)

dev/dt/driver.c

@@ -0,0 +1,96 @@
+#define pr_fmt(fmt) "fdt: " fmt
+
+#include <zinnia/alloc.h>
+#include <zinnia/fdt.h>
+#include <zinnia/init.h>
+#include <zinnia/print.h>
+#include <zinnia/spin.h>
+#include <zinnia/vec.h>
+#include <string.h>
+
+static struct fdt tree;
+static bool tree_valid = false;
+
+static struct spinlock driver_lock = {};
+static vec(struct fdt_driver*) drivers = {};
+
+struct fdt* fdt_get() {
+    return tree_valid ? &tree : nullptr;
+}
+
+static const struct fdt_match* fdt_match_table(
+    const struct fdt_match* table,
+    size_t num_matches,
+    struct fdt_node node
+) {
+    for (size_t i = 0; i < num_matches; i++) {
+        if (fdt_node_is_compatible(node, table[i].compatible))
+            return &table[i];
+    }
+    return nullptr;
+}
+
+errno_t fdt_driver_register(struct fdt_driver* driver) {
+    if (driver->match == nullptr || driver->num_matches == 0) {
+        log_warn("Driver \"%s\" does not define any matches, ignoring\n", driver->name);
+        return 0;
+    }
+
+    if (!tree_valid)
+        return ENODEV;
+
+    spin_lock(&driver_lock);
+    vec_foreach(&drivers, i) {
+        if (strcmp(vec_elem_get(&drivers, i)->name, driver->name) == 0) {
+            spin_unlock(&driver_lock);
+            log_warn("Driver \"%s\" is already registered\n", driver->name);
+            return EEXIST;
+        }
+    }
+    errno_t status = vec_push(&drivers, driver);
+    spin_unlock(&driver_lock);
+    if (status != 0)
+        return status;
+
+    log("Registered platform driver \"%s\" with %zu match%s\n",
+        driver->name,
+        driver->num_matches,
+        driver->num_matches == 1 ? "" : "es");
+    for (size_t i = 0; i < driver->num_matches; i++)
+        log("  [%zu] = \"%s\"\n", i, driver->match[i].compatible);
+
+    for (struct fdt_node node = fdt_root(&tree); node.tree; node = fdt_next_node(node)) {
+        const struct fdt_match* match = fdt_match_table(driver->match, driver->num_matches, node);
+        if (match == nullptr)
+            continue;
+
+        log("Matched driver \"%s\" on rule [%zu]\n", driver->name, (size_t)(match - driver->match));
+
+        status = driver->probe(node, match);
+        if (status != 0)
+            log_warn("%s failed to probe: %i\n", driver->name, status);
+    }
+
+    return 0;
+}
+
+[[__init]]
+static bool fdt_stage_init(struct boot_info* info) {
+    if (!info->dtb)
+        return false;
+
+    const void* blob = HHDM_PTR(info->dtb);
+    if (!fdt_init(&tree, blob, info->dtb_size)) {
+        log_warn("Unable to parse the device tree blob\n");
+        return false;
+    }
+    tree_valid = true;
+
+    struct fdt_prop model = fdt_property(fdt_root(&tree), "model");
+    if (model.tree && model.length)
+        log("Running on \"%.*s\"\n", (int)model.length, (const char*)model.data);
+
+    return true;
+}
+INIT_TASK(fdt_stage, "dev.dt", fdt_stage_init);
+INIT_DEPENDS(fdt_stage, mem_stage);

dev/dt/fdt.c

@@ -0,0 +1,281 @@
+#include <zinnia/fdt.h>
+#include <string.h>
+
+uint32_t fdt_read_u32(const void* data) {
+    const uint8_t* p = data;
+    return (uint32_t)p[0] << 24 | (uint32_t)p[1] << 16 | (uint32_t)p[2] << 8 | p[3];
+}
+
+uint64_t fdt_read_u64(const void* data) {
+    const uint8_t* p = data;
+    return (uint64_t)fdt_read_u32(p) << 32 | fdt_read_u32(p + 4);
+}
+
+static bool range_valid(size_t offset, size_t length, size_t total) {
+    return offset <= total && length <= total - offset;
+}
+
+struct token {
+    uint32_t kind;
+    size_t next;
+    const char* name;
+    const void* data;
+    size_t length;
+};
+
+static bool read_token(struct fdt* tree, size_t offset, struct token* token) {
+    if (!range_valid(offset, 4, tree->structs_len) || offset % 4)
+        return false;
+    *token = (struct token){.kind = fdt_read_u32(tree->structs + offset), .next = offset + 4};
+    if (token->kind == FDT_BEGIN_NODE) {
+        token->name = (const char*)tree->structs + token->next;
+        size_t left = tree->structs_len - token->next;
+        size_t length = strnlen(token->name, left);
+        if (length == left)
+            return false;
+        token->next += (length + 1 + 3) & ~(size_t)3;
+    } else if (token->kind == FDT_PROP) {
+        if (!range_valid(token->next, 8, tree->structs_len))
+            return false;
+        token->length = fdt_read_u32(tree->structs + token->next);
+        size_t name_offset = fdt_read_u32(tree->structs + token->next + 4);
+        token->next += 8;
+        if (name_offset >= tree->strings_len || !range_valid(token->next, token->length, tree->structs_len))
+            return false;
+        token->name = (const char*)tree->strings + name_offset;
+        size_t left = tree->strings_len - name_offset;
+        if (strnlen(token->name, left) == left || !*token->name)
+            return false;
+        token->data = tree->structs + token->next;
+        token->next += (token->length + 3) & ~(size_t)3;
+    } else if (token->kind != FDT_END_NODE && token->kind != FDT_NOP && token->kind != FDT_END) {
+        return false;
+    }
+    return token->next <= tree->structs_len;
+}
+
+bool fdt_init(struct fdt* tree, const void* data, size_t length) {
+    if (!tree)
+        return false;
+    *tree = (struct fdt){};
+    if (!data || length < sizeof(struct fdt_header))
+        return false;
+    const uint8_t* blob = data;
+    size_t total = fdt_read_u32(blob + 4);
+    size_t structs = fdt_read_u32(blob + 8);
+    size_t strings = fdt_read_u32(blob + 12);
+    size_t reserves = fdt_read_u32(blob + 16);
+    size_t strings_len = fdt_read_u32(blob + 32);
+    size_t structs_len = fdt_read_u32(blob + 36);
+    uint32_t version = fdt_read_u32(blob + 20);
+    uint32_t compat = fdt_read_u32(blob + 24);
+    if (fdt_read_u32(blob) != FDT_MAGIC || total > length || total < sizeof(struct fdt_header) || version < 17 ||
+        compat > 17 || compat > version || structs % 4 || reserves % 8 || structs < sizeof(struct fdt_header) ||
+        strings < sizeof(struct fdt_header) || reserves < sizeof(struct fdt_header) ||
+        !range_valid(structs, structs_len, total) || !range_valid(strings, strings_len, total) ||
+        (structs < strings + strings_len && strings < structs + structs_len))
+        return false;
+    size_t reserved_end = reserves;
+    for (;;) {
+        if (!range_valid(reserved_end, 16, total))
+            return false;
+        bool end = !fdt_read_u64(blob + reserved_end) && !fdt_read_u64(blob + reserved_end + 8);
+        reserved_end += 16;
+        if (end)
+            break;
+    }
+    if ((reserves < structs + structs_len && structs < reserved_end) ||
+        (reserves < strings + strings_len && strings < reserved_end))
+        return false;
+    struct fdt candidate = {
+        .blob = blob,
+        .total_size = total,
+        .version = version,
+        .compat_version = compat,
+        .boot_cpuid = fdt_read_u32(blob + 28),
+        .structs = blob + structs,
+        .structs_len = structs_len,
+        .strings = blob + strings,
+        .strings_len = strings_len,
+    };
+    size_t depth = 0;
+    bool started = false;
+    bool children[64] = {};
+    for (size_t offset = 0; offset < structs_len;) {
+        struct token token;
+        if (!read_token(&candidate, offset, &token))
+            return false;
+        if (token.kind == FDT_BEGIN_NODE) {
+            if (depth == 64 || (!depth && (started || *token.name)) || (depth && !*token.name))
+                return false;
+            if (depth)
+                children[depth - 1] = true;
+            children[depth++] = false;
+            started = true;
+        } else if (token.kind == FDT_END_NODE) {
+            if (!depth)
+                return false;
+            depth--;
+        } else if (token.kind == FDT_PROP) {
+            if (!depth || children[depth - 1])
+                return false;
+        } else if (token.kind == FDT_END) {
+            if (!started || depth || token.next != structs_len)
+                return false;
+            *tree = candidate;
+            return true;
+        }
+        offset = token.next;
+    }
+    return false;
+}
+
+struct fdt_node fdt_root(struct fdt* tree) {
+    struct token token;
+    size_t offset = 0;
+    if (tree && tree->blob) {
+        while (read_token(tree, offset, &token)) {
+            if (token.kind == FDT_BEGIN_NODE)
+                return (struct fdt_node){tree, offset};
+            if (token.kind != FDT_NOP)
+                break;
+            offset = token.next;
+        }
+    }
+    return (struct fdt_node){};
+}
+
+static struct fdt_node find_child(struct fdt_node node, const char* name, size_t length) {
+    struct token token;
+    if (!node.tree || !read_token(node.tree, node.offset, &token) || token.kind != FDT_BEGIN_NODE)
+        return (struct fdt_node){};
+    size_t depth = 0;
+    for (size_t offset = token.next; read_token(node.tree, offset, &token); offset = token.next) {
+        if (token.kind == FDT_BEGIN_NODE) {
+            if (!depth && strlen(token.name) == length && !memcmp(token.name, name, length))
+                return (struct fdt_node){node.tree, offset};
+            depth++;
+        } else if (token.kind == FDT_END_NODE) {
+            if (!depth)
+                break;
+            depth--;
+        }
+    }
+    return (struct fdt_node){};
+}
+
+struct fdt_node fdt_find(struct fdt* tree, const char* path) {
+    if (!path || *path != '/')
+        return (struct fdt_node){};
+    struct fdt_node node = fdt_root(tree);
+    path++;
+    while (*path && node.tree) {
+        size_t length = 0;
+        while (path[length] && path[length] != '/')
+            length++;
+        if (!length)
+            return (struct fdt_node){};
+        node = find_child(node, path, length);
+        path += length;
+        if (*path == '/')
+            path++;
+    }
+    return node;
+}
+
+struct fdt_prop fdt_property(struct fdt_node node, const char* name) {
+    struct token token;
+    if (!node.tree || !name || !read_token(node.tree, node.offset, &token) || token.kind != FDT_BEGIN_NODE)
+        return (struct fdt_prop){};
+    for (size_t offset = token.next; read_token(node.tree, offset, &token); offset = token.next) {
+        if (token.kind == FDT_PROP && !strcmp(token.name, name))
+            return (struct fdt_prop){node.tree, token.data, token.length};
+        if (token.kind == FDT_BEGIN_NODE || token.kind == FDT_END_NODE)
+            break;
+    }
+    return (struct fdt_prop){};
+}
+
+bool fdt_property_u32(struct fdt_node node, const char* name, uint32_t* value) {
+    struct fdt_prop property = fdt_property(node, name);
+    if (!property.tree || property.length != 4 || !value)
+        return false;
+    *value = fdt_read_u32(property.data);
+    return true;
+}
+
+bool fdt_property_u64(struct fdt_node node, const char* name, uint64_t* value) {
+    struct fdt_prop property = fdt_property(node, name);
+    if (!property.tree || property.length != 8 || !value)
+        return false;
+    *value = fdt_read_u64(property.data);
+    return true;
+}
+
+struct fdt_node fdt_next_node(struct fdt_node node) {
+    struct token token;
+    if (!node.tree || !read_token(node.tree, node.offset, &token))
+        return (struct fdt_node){};
+    for (size_t offset = token.next; read_token(node.tree, offset, &token); offset = token.next) {
+        if (token.kind == FDT_BEGIN_NODE)
+            return (struct fdt_node){node.tree, offset};
+        if (token.kind == FDT_END)
+            break;
+    }
+    return (struct fdt_node){};
+}
+
+bool fdt_node_is_compatible(struct fdt_node node, const char* compatible) {
+    struct fdt_prop property = fdt_property(node, "compatible");
+    const char* data = property.data;
+    for (size_t i = 0; i < property.length;) {
+        size_t length = strnlen(data + i, property.length - i);
+        if (length == property.length - i)
+            break;
+        if (!strcmp(data + i, compatible))
+            return true;
+        i += length + 1;
+    }
+    return false;
+}
+
+static uint64_t read_cells(const uint8_t* data, uint32_t cells) {
+    uint64_t value = 0;
+    for (uint32_t i = 0; i < cells; i++)
+        value = value << 32 | fdt_read_u32(data + i * 4);
+    return value;
+}
+
+bool fdt_node_reg(struct fdt_node node, size_t index, phys_t* addr, size_t* size) {
+    if (!node.tree)
+        return false;
+    struct fdt_node root = fdt_root(node.tree);
+    uint32_t addr_cells = 2;
+    uint32_t size_cells = 2;
+    fdt_property_u32(root, "#address-cells", &addr_cells);
+    fdt_property_u32(root, "#size-cells", &size_cells);
+    if (addr_cells > 2 || size_cells > 2)
+        return false;
+
+    struct fdt_prop reg = fdt_property(node, "reg");
+    const size_t stride = (addr_cells + size_cells) * 4;
+    if (!reg.tree || index >= reg.length / stride)
+        return false;
+
+    const uint8_t* entry = (const uint8_t*)reg.data + index * stride;
+    if (addr)
+        *addr = read_cells(entry, addr_cells);
+    if (size)
+        *size = read_cells(entry + addr_cells * 4, size_cells);
+    return true;
+}
+
+struct fdt_node fdt_find_compatible(struct fdt* tree, const char* compatible) {
+    if (!tree || !tree->blob || !compatible)
+        return (struct fdt_node){};
+    for (struct fdt_node node = fdt_root(tree); node.tree; node = fdt_next_node(node)) {
+        if (fdt_node_is_compatible(node, compatible))
+            return node;
+    }
+    return (struct fdt_node){};
+}

dev/dt/meson.build

@@ -0,0 +1,4 @@
+kernel_sources += files(
+    'driver.c',
+    'fdt.c',
+)

dev/meson.build

@@ -0,0 +1,14 @@
+subdir('common')
+subdir('block')
+subdir('dt')
+subdir('video')
+
+if kconfig.get('CONFIG_PCI', 'n') == 'y'
+    subdir('pci')
+endif
+
+if kconfig.get('CONFIG_ACPI', 'n') == 'y'
+    subdir('acpi')
+endif
+
+module_lds = meson.current_source_dir() / 'module.ld'

dev/module.ld

@@ -0,0 +1,114 @@
+/* Linker script for kernel modules */
+
+ENTRY(__module_entry)
+
+PHDRS
+{
+    text        PT_LOAD     FLAGS(5);
+    rodata      PT_LOAD     FLAGS(4);
+    data        PT_LOAD     FLAGS(6);
+    dynamic     PT_DYNAMIC  FLAGS(6);
+    modversion  0x60000001;
+    modauthor   0x60000002;
+    moddesc     0x60000003;
+    modlicense  0x60000004;
+    modcmdline  0x60000005;
+    modexit     0x60000006;
+    modmatch    0x60000007;
+}
+
+SECTIONS
+{
+    . = ALIGN(CONSTANT(MAXPAGESIZE));
+
+    /* Code */
+    .text : {
+        *(.init .init.*)
+        *(.text .text.*)
+        *(.fini .fini.*)
+        *(.plt .plt.*)
+    } :text
+
+    . = ALIGN(CONSTANT(MAXPAGESIZE));
+
+    /* Read-only data */
+    .rodata : {
+        *(.rodata .rodata.*)
+        *(.hash .hash.*)
+        *(.got .got.*)
+        *(.got.plt .got.plt.*)
+    } :rodata
+
+    .mod.version : {
+        KEEP(*(.mod.version))
+    } :rodata :modversion
+
+    .mod.author : {
+        KEEP(*(.mod.author))
+    } :rodata :modauthor
+
+    .mod.desc : {
+        KEEP(*(.mod.desc))
+    } :rodata :moddesc
+
+    .mod.license : {
+        KEEP(*(.mod.license))
+    } :rodata :modlicense
+
+    .cmdline : {
+        KEEP(*(.cmdline))
+    } :rodata :modcmdline
+
+    .mod.exit : {
+        KEEP(*(.mod.exit))
+    } :rodata :modexit
+
+    .mod.match : {
+        KEEP(*(.mod.match))
+    } :rodata :modmatch
+
+    . = ALIGN(CONSTANT(MAXPAGESIZE));
+
+    /* Read-Write data */
+    .data : {
+        *(.data)
+        *(.data.*)
+    } :data
+
+    /* Zero-initialized memory */
+    .bss : {
+        *(.*bss .*bss.*)
+        *(COMMON)
+    } :data
+
+    .dynsym : {
+        *(.dynsym .dynsym.*)
+    } :data
+
+    .dynstr : {
+        *(.dynstr .dynstr.*)
+    } :data
+
+    .rela.dyn : {
+        *(.rela.dyn .rela.dyn.*)
+    } :data
+
+    .relr.dyn : {
+        *(.relr.dyn .relr.dyn.*)
+    } :data
+
+    /* Dynamic tags */
+    .dynamic : {
+        *(.dynamic)
+    } :data :dynamic
+
+    /DISCARD/ :
+    {
+        *(.comment*)
+        *(.eh_frame*)
+        *(.rel.eh_frame*)
+        *(.gcc_except_table*)
+        *(.note*)
+        *(.interp)
+    }
+}

dev/pci/Kconfig

@@ -0,0 +1,7 @@
+menu "PCI bus drivers"
+
+config PCI
+  bool "PCI core drivers"
+  default y
+
+endmenu

dev/pci/core.c

@@ -0,0 +1,375 @@
+#define pr_fmt(fmt) "pci: " fmt
+
+#include <zinnia/alloc.h>
+#include <zinnia/init.h>
+#include <zinnia/module.h>
+#include <zinnia/pci.h>
+#include <zinnia/print.h>
+#include <zinnia/spin.h>
+#include <zinnia/vec.h>
+#include <string.h>
+
+static struct spinlock access_lock = {};
+static vec(struct pci_access*) accesses = {};
+
+static struct spinlock device_lock = {};
+static vec(struct pci_device*) devices = {};
+static vec(struct pci_driver*) drivers = {};
+
+errno_t pci_access_register(struct pci_access* access) {
+    spin_lock(&access_lock);
+    errno_t status = vec_push(&accesses, access);
+    spin_unlock(&access_lock);
+    return status;
+}
+
+static bool pci_access_decodes(const struct pci_access* access, const struct pci_address* addr) {
+    return access->domain == addr->domain && addr->bus >= access->start_bus && addr->bus <= access->end_bus;
+}
+
+struct pci_access* pci_access_find(const struct pci_address* addr) {
+    struct pci_access* found = nullptr;
+
+    spin_lock(&access_lock);
+    vec_foreach(&accesses, i) {
+        struct pci_access* access = vec_elem_get(&accesses, i);
+        if (!pci_access_decodes(access, addr))
+            continue;
+        if (found == nullptr || access->priority > found->priority)
+            found = access;
+    }
+    spin_unlock(&access_lock);
+
+    return found;
+}
+
+static uint32_t cfg_read32(struct pci_access* access, const struct pci_address* addr, uint16_t offset) {
+    return access->read32(access, addr, offset & ~3);
+}
+
+static void cfg_write32(struct pci_access* access, const struct pci_address* addr, uint16_t offset, uint32_t value) {
+    access->write32(access, addr, offset & ~3, value);
+}
+
+uint32_t pci_read32(struct pci_device* dev, uint16_t offset) {
+    return cfg_read32(dev->access, &dev->address, offset);
+}
+
+uint16_t pci_read16(struct pci_device* dev, uint16_t offset) {
+    return pci_read32(dev, offset) >> ((offset & 2) * 8);
+}
+
+uint8_t pci_read8(struct pci_device* dev, uint16_t offset) {
+    return pci_read32(dev, offset) >> ((offset & 3) * 8);
+}
+
+void pci_write32(struct pci_device* dev, uint16_t offset, uint32_t value) {
+    cfg_write32(dev->access, &dev->address, offset, value);
+}
+
+void pci_write16(struct pci_device* dev, uint16_t offset, uint16_t value) {
+    uint32_t shift = (offset & 2) * 8;
+    uint32_t reg = pci_read32(dev, offset);
+    reg &= ~(0xffffu << shift);
+    reg |= (uint32_t)value << shift;
+    pci_write32(dev, offset, reg);
+}
+
+void pci_write8(struct pci_device* dev, uint16_t offset, uint8_t value) {
+    uint32_t shift = (offset & 3) * 8;
+    uint32_t reg = pci_read32(dev, offset);
+    reg &= ~(0xffu << shift);
+    reg |= (uint32_t)value << shift;
+    pci_write32(dev, offset, reg);
+}
+
+errno_t pci_bar_get(struct pci_device* dev, size_t index, struct pci_bar* out) {
+    if (index >= PCI_NUM_BARS)
+        return EINVAL;
+
+    uint16_t bar_offset = PCI_BAR0 + index * sizeof(uint32_t);
+    uint16_t high_offset = bar_offset + sizeof(uint32_t);
+    uint32_t bar = pci_read32(dev, bar_offset);
+
+    bool is_mmio = (bar & 0x1) == 0;
+    bool is_mmio64 = is_mmio && ((bar >> 1) & 0x3) == 0x2;
+    bool is_prefetchable = is_mmio && (bar & (1 << 3));
+    bool is_64bit_pair = is_mmio64 && index + 1 < PCI_NUM_BARS;
+
+    uint16_t command = pci_read16(dev, PCI_COMMAND);
+    pci_write16(dev, PCI_COMMAND, command & ~(PCI_COMMAND_IO | PCI_COMMAND_MEM));
+
+    uint32_t high = is_64bit_pair ? pci_read32(dev, high_offset) : 0;
+
+    pci_write32(dev, bar_offset, 0xffff'ffff);
+    if (is_64bit_pair)
+        pci_write32(dev, high_offset, 0xffff'ffff);
+
+    uint32_t mask_low = pci_read32(dev, bar_offset);
+    uint32_t mask_high = is_64bit_pair ? pci_read32(dev, high_offset) : 0;
+
+    pci_write32(dev, bar_offset, bar);
+    if (is_64bit_pair)
+        pci_write32(dev, high_offset, high);
+
+    pci_write16(dev, PCI_COMMAND, command);
+
+    uint64_t addr_mask = is_mmio ? ~0xfull : ~0x3ull;
+    uint64_t raw = (uint64_t)mask_high << 32 | mask_low;
+    uint64_t masked = raw & addr_mask & (is_64bit_pair ? UINT64_MAX : UINT32_MAX);
+
+    struct pci_bar result = {
+        .size = masked == 0 ? 0 : (size_t)1 << __builtin_ctzll(masked),
+        .prefetchable = is_prefetchable,
+    };
+
+    if (is_mmio && is_64bit_pair) {
+        result.type = PCI_BAR_MMIO64;
+        result.address = (phys_t)high << 32 | (bar & 0xffff'fff0);
+    } else if (is_mmio) {
+        result.type = PCI_BAR_MMIO32;
+        result.address = bar & 0xffff'fff0;
+    } else {
+        result.type = PCI_BAR_IO;
+        result.address = (uint16_t)(bar & 0xffff'fffc);
+    }
+
+    if (result.address == 0)
+        return ENOENT;
+
+    *out = result;
+    return 0;
+}
+
+uint8_t pci_cap_next(struct pci_device* dev, uint8_t cur) {
+    uint8_t ptr;
+    if (cur == 0) {
+        if (!(pci_read16(dev, PCI_STATUS) & PCI_STATUS_CAP_LIST))
+            return 0;
+        ptr = pci_read8(dev, PCI_CAP_PTR) & ~3;
+    } else {
+        ptr = (pci_read32(dev, cur) >> 8) & ~3;
+    }
+
+    if (ptr == 0)
+        return 0;
+
+    if ((pci_read32(dev, ptr) & 0xff) == 0xff)
+        return 0;
+
+    return ptr;
+}
+
+uint8_t pci_cap_find(struct pci_device* dev, uint8_t id) {
+    for (uint8_t cap = pci_cap_next(dev, 0); cap != 0; cap = pci_cap_next(dev, cap)) {
+        if (pci_read8(dev, cap) == id)
+            return cap;
+    }
+    return 0;
+}
+
+static void pci_device_name(const struct pci_device* dev, char buf[static 18]) {
+    ksnprintf(buf, 18, "pci-" PCI_ADDR_FMT, PCI_ADDR_ARGS(&dev->address));
+}
+
+static bool scan_function(struct pci_access* access, struct pci_address addr) {
+    uint32_t reg0 = cfg_read32(access, &addr, PCI_VENDOR_ID);
+    uint16_t vendor_id = reg0;
+    uint16_t device_id = reg0 >> 16;
+
+    if (vendor_id == 0xffff || vendor_id == 0)
+        return false;
+    if (device_id == 0xffff || device_id == 0)
+        return false;
+
+    struct pci_device* dev = mem_alloc(sizeof(*dev), 0);
+    if (dev == nullptr) {
+        log_err("Out of memory while scanning " PCI_ADDR_FMT "\n", PCI_ADDR_ARGS(&addr));
+        return false;
+    }
+
+    dev->address = addr;
+    dev->access = access;
+    dev->id.vendor_id = vendor_id;
+    dev->id.device_id = device_id;
+    dev->class.prog_if = pci_read8(dev, PCI_PROG_IF);
+    dev->class.subclass = pci_read8(dev, PCI_SUBCLASS);
+    dev->class.class = pci_read8(dev, PCI_CLASS);
+    dev->header_type = pci_read8(dev, PCI_HEADER_TYPE);
+
+    if ((dev->header_type & PCI_HEADER_TYPE_MASK) == 0) {
+        dev->id.subvendor_id = pci_read16(dev, PCI_SUBSYS_VENDOR_ID);
+        dev->id.subdevice_id = pci_read16(dev, PCI_SUBSYS_ID);
+    }
+
+    pci_log(
+        dev,
+        "<id = %.4hx:%.4hx, class = %.2hhx:%.2hhx:%.2hhx>\n",
+        dev->id.vendor_id,
+        dev->id.device_id,
+        dev->class.class,
+        dev->class.subclass,
+        dev->class.prog_if
+    );
+
+    if (vec_push(&devices, dev) != 0) {
+        mem_free(dev);
+        return false;
+    }
+
+    return true;
+}
+
+static void scan_slot(struct pci_access* access, struct pci_address addr) {
+    if (!scan_function(access, addr))
+        return;
+
+    if (!(vec_elem_get(&devices, vec_length(&devices) - 1)->header_type & PCI_HEADER_TYPE_MULTIFUNCTION))
+        return;
+
+    for (addr.function = 1; addr.function < PCI_NUM_FUNCTIONS; addr.function++)
+        scan_function(access, addr);
+}
+
+static void format_match_id(char buf[static 5], uint16_t value) {
+    if (value == PCI_ANY_ID)
+        ksnprintf(buf, 5, "****");
+    else
+        ksnprintf(buf, 5, "%.4hx", value);
+}
+
+static void format_match_class(char buf[static 3], uint8_t value) {
+    if (value == PCI_ANY_CLASS)
+        ksnprintf(buf, 3, "**");
+    else
+        ksnprintf(buf, 3, "%.2hhx", value);
+}
+
+static void format_match(const struct pci_match* match, char* buf, size_t size) {
+    char vendor[5], device[5], class[3], subclass[3], prog_if[3];
+    format_match_id(vendor, match->vendor_id);
+    format_match_id(device, match->device_id);
+    format_match_class(class, match->class);
+    format_match_class(subclass, match->subclass);
+    format_match_class(prog_if, match->prog_if);
+    ksnprintf(buf, size, "<id = %s:%s, class = %s:%s:%s>", vendor, device, class, subclass, prog_if);
+}
+
+static bool pci_match_device(const struct pci_match* m, const struct pci_device* dev) {
+    return (m->vendor_id == PCI_ANY_ID || m->vendor_id == dev->id.vendor_id) &&
+        (m->device_id == PCI_ANY_ID || m->device_id == dev->id.device_id) &&
+        (m->class == PCI_ANY_CLASS || m->class == dev->class.class) &&
+        (m->subclass == PCI_ANY_CLASS || m->subclass == dev->class.subclass) &&
+        (m->prog_if == PCI_ANY_CLASS || m->prog_if == dev->class.prog_if);
+}
+
+// Returns the first entry that matches, or nullptr.
+static const struct pci_match* pci_match_table(
+    const struct pci_match* table,
+    size_t num_matches,
+    const struct pci_device* dev
+) {
+    for (size_t i = 0; i < num_matches; i++) {
+        if (pci_match_device(&table[i], dev))
+            return &table[i];
+    }
+    return nullptr;
+}
+
+errno_t pci_driver_register(struct pci_driver* driver) {
+    if (driver->match == nullptr || driver->num_matches == 0) {
+        log_warn("Driver \"%s\" does not define any matches, ignoring\n", driver->name);
+        return 0;
+    }
+
+    spin_lock(&device_lock);
+
+    vec_foreach(&drivers, i) {
+        if (strcmp(vec_elem_get(&drivers, i)->name, driver->name) == 0) {
+            spin_unlock(&device_lock);
+            log_warn("Driver \"%s\" is already registered\n", driver->name);
+            return EEXIST;
+        }
+    }
+
+    errno_t status = vec_push(&drivers, driver);
+    spin_unlock(&device_lock);
+    if (status != 0)
+        return status;
+
+    log("Registered PCI driver \"%s\" with %zu match%s\n",
+        driver->name,
+        driver->num_matches,
+        driver->num_matches == 1 ? "" : "es");
+    for (size_t i = 0; i < driver->num_matches; i++) {
+        char rule[48];
+        format_match(&driver->match[i], rule, sizeof(rule));
+        log("  [%zu] = %s\n", i, rule);
+    }
+
+    for (size_t i = 0;; i++) {
+        spin_lock(&device_lock);
+        if (i >= vec_length(&devices)) {
+            spin_unlock(&device_lock);
+            break;
+        }
+
+        struct pci_device* dev = vec_elem_get(&devices, i);
+        const struct pci_match* match = nullptr;
+        if (dev->driver == nullptr) {
+            match = pci_match_table(driver->match, driver->num_matches, dev);
+            if (match != nullptr)
+                dev->driver = driver;
+        }
+        spin_unlock(&device_lock);
+
+        if (match == nullptr)
+            continue;
+
+        pci_log(dev, "Matched driver \"%s\" on rule [%zu]\n", driver->name, (size_t)(match - driver->match));
+
+        status = driver->probe(dev, match);
+        if (status != 0) {
+            pci_log_warn(dev, "%s failed to probe: %i\n", driver->name, status);
+            spin_lock(&device_lock);
+            dev->driver = nullptr;
+            spin_unlock(&device_lock);
+        }
+    }
+
+    return 0;
+}
+
+[[__init]]
+static void pci_stage_init(struct boot_info*) {
+    if (vec_is_empty(&accesses)) {
+        log_warn("No configuration space access method available\n");
+        return;
+    }
+
+    log("Scanning PCI devices\n");
+
+    spin_lock(&device_lock);
+    vec_foreach(&accesses, i) {
+        struct pci_access* access = vec_elem_get(&accesses, i);
+        for (uint32_t bus = access->start_bus; bus <= access->end_bus; bus++) {
+            for (uint8_t slot = 0; slot < PCI_NUM_SLOTS; slot++) {
+                struct pci_address addr = {
+                    .domain = access->domain,
+                    .bus = bus,
+                    .device = slot,
+                };
+
+                if (pci_access_find(&addr) != access)
+                    continue;
+
+                scan_slot(access, addr);
+            }
+        }
+    }
+    spin_unlock(&device_lock);
+
+    log("Found %zu device(s)\n", vec_length(&devices));
+}
+INIT_TASK(pci_stage, "dev.pci", pci_stage_init);
+INIT_DEPENDS(pci_stage, mem_stage);

dev/pci/ecam.c

@@ -0,0 +1,76 @@
+#define pr_fmt(fmt) "pci: " fmt
+
+#include <zinnia/alloc.h>
+#include <zinnia/mmio.h>
+#include <zinnia/pci.h>
+#include <zinnia/pmap.h>
+#include <zinnia/print.h>
+#include <zinnia/utils.h>
+#include <zinnia/virt.h>
+#include <zinnia/vma.h>
+#include <arch/mem.h>
+
+struct pci_ecam {
+    struct pci_access access;
+    void* base;
+};
+
+static void* ecam_ptr(struct pci_access* self, const struct pci_address* addr, uint16_t offset) {
+    struct pci_ecam* ecam = containerof(self, struct pci_ecam, access);
+    size_t index = (size_t)(addr->bus - self->start_bus) << 20 | (size_t)(addr->device & 0x1f) << 15 |
+        (size_t)(addr->function & 0x7) << 12 | (offset & 0xffc);
+    return (uint8_t*)ecam->base + index;
+}
+
+static uint32_t ecam_read32(struct pci_access* self, const struct pci_address* addr, uint16_t offset) {
+    return mmio_read32(ecam_ptr(self, addr, offset));
+}
+
+static void ecam_write32(struct pci_access* self, const struct pci_address* addr, uint16_t offset, uint32_t value) {
+    mmio_write32(ecam_ptr(self, addr, offset), value);
+}
+
+errno_t pci_ecam_register(phys_t base, uint16_t domain, uint8_t start_bus, uint8_t end_bus) {
+    if (end_bus < start_bus)
+        return EINVAL;
+
+    size_t length = ((size_t)(end_bus - start_bus) + 1) << 20;
+    phys_t phys = base + ((phys_t)start_bus << 20);
+
+    uintptr_t vaddr = vm_alloc(length);
+    if (!vaddr)
+        return ENOMEM;
+
+    for (size_t i = 0; i < length; i += arch_mem_page_size()) {
+        errno_t status = pmap_map(&kernel_vma.pmap, vaddr + i, phys + i, PTE_READ | PTE_WRITE, CACHE_MMIO);
+        if (status != 0)
+            return status;
+    }
+
+    struct pci_ecam* ecam = mem_alloc(sizeof(*ecam), 0);
+    if (ecam == nullptr)
+        return ENOMEM;
+
+    *ecam = (struct pci_ecam){
+        .access =
+            {
+                .name = "ecam",
+                .domain = domain,
+                .start_bus = start_bus,
+                .end_bus = end_bus,
+                .priority = PCI_ACCESS_PRIO_ECAM,
+                .read32 = ecam_read32,
+                .write32 = ecam_write32,
+            },
+        .base = (void*)vaddr,
+    };
+
+    errno_t status = pci_access_register(&ecam->access);
+    if (status != 0) {
+        mem_free(ecam);
+        return status;
+    }
+
+    log("ECAM for %.4hx:%.2hhx - %.4hx:%.2hhx at %p\n", domain, start_bus, domain, end_bus, (void*)phys);
+    return 0;
+}

dev/pci/meson.build

@@ -0,0 +1,4 @@
+kernel_sources += files(
+    'core.c',
+    'ecam.c',
+)

dev/video/Kconfig

@@ -0,0 +1,9 @@
+menu "Video Drivers"
+
+config FBCON
+  bool "Framebuffer console"
+  default y
+  help
+    Adds a basic console that can draw on a framebuffer passed by firmware.
+
+endmenu

dev/video/fbcon/fbcon.c

@@ -0,0 +1,205 @@
+#include <zinnia/alloc.h>
+#include <zinnia/assert.h>
+#include <zinnia/console.h>
+#include <zinnia/init.h>
+#include <zinnia/pmap.h>
+#include <zinnia/sched.h>
+#include <zinnia/utils.h>
+#include <zinnia/vma.h>
+#include <stdint.h>
+#include <string.h>
+
+static const uint8_t fbcon_font[] = {
+#embed "fbcon_font.bin"
+};
+
+constexpr size_t FONT_WIDTH = 8;
+constexpr size_t FONT_HEIGHT = 12;
+constexpr uint32_t FG_COLOR = 0xaaaaaa;
+constexpr uint32_t BG_COLOR = 0x000000;
+
+enum esc_state {
+    ESC_NONE,
+    ESC_START,
+    ESC_CSI,
+};
+
+static struct {
+    struct boot_framebuffer fb;
+    uint32_t* back;
+    uint32_t fg, bg;
+    size_t cols, rows;
+    size_t offset_x, offset_y;
+    size_t cx, cy;
+    enum esc_state esc;
+} fbcon;
+
+static inline uint8_t* fb_ptr() {
+    return HHDM_PTR(fbcon.fb.base);
+}
+
+static inline uint32_t* back_row(size_t y) {
+    return fbcon.back + y * fbcon.fb.width;
+}
+
+static void flush_rect(size_t x, size_t y, size_t w, size_t h) {
+    for (size_t j = 0; j < h; j++)
+        memcpy((uint32_t*)(fb_ptr() + (y + j) * fbcon.fb.pitch) + x, back_row(y + j) + x, w * sizeof(uint32_t));
+}
+
+static uint32_t pack_color(uint32_t rgb) {
+    const struct boot_framebuffer* fb = &fbcon.fb;
+    uint32_t r = (rgb >> 16) & 0xff;
+    uint32_t g = (rgb >> 8) & 0xff;
+    uint32_t b = rgb & 0xff;
+    return ((r >> (8 - fb->red.size)) << fb->red.shift) | ((g >> (8 - fb->green.size)) << fb->green.shift) |
+        ((b >> (8 - fb->blue.size)) << fb->blue.shift);
+}
+
+static void fill_rect(size_t x, size_t y, size_t w, size_t h, uint32_t color) {
+    for (size_t j = 0; j < h; j++) {
+        uint32_t* row = back_row(y + j) + x;
+        for (size_t i = 0; i < w; i++)
+            row[i] = color;
+    }
+    flush_rect(x, y, w, h);
+}
+
+static void clear_screen() {
+    fill_rect(0, 0, fbcon.fb.width, fbcon.fb.height, fbcon.bg);
+    fbcon.cx = fbcon.cy = 0;
+}
+
+static void draw_glyph(size_t col, size_t row, uint8_t ch) {
+    const uint8_t* glyph = &fbcon_font[ch * FONT_HEIGHT];
+    size_t x = fbcon.offset_x + col * FONT_WIDTH;
+    size_t y = fbcon.offset_y + row * FONT_HEIGHT;
+
+    for (size_t j = 0; j < FONT_HEIGHT; j++) {
+        uint32_t* line = back_row(y + j) + x;
+        for (size_t i = 0; i < FONT_WIDTH; i++)
+            line[i] = (glyph[j] & (0x80 >> i)) ? fbcon.fg : fbcon.bg;
+    }
+    flush_rect(x, y, FONT_WIDTH, FONT_HEIGHT);
+}
+
+static void scroll_up() {
+    const size_t width = fbcon.fb.width;
+    const size_t text_y = fbcon.offset_y;
+    const size_t text_h = fbcon.rows * FONT_HEIGHT;
+
+    memmove(back_row(text_y), back_row(text_y + FONT_HEIGHT), (text_h - FONT_HEIGHT) * width * sizeof(uint32_t));
+    for (size_t j = text_y + text_h - FONT_HEIGHT; j < text_y + text_h; j++) {
+        uint32_t* row = back_row(j);
+        for (size_t i = 0; i < width; i++)
+            row[i] = fbcon.bg;
+    }
+    flush_rect(0, text_y, width, text_h);
+}
+
+static void newline() {
+    fbcon.cx = 0;
+    if (++fbcon.cy >= fbcon.rows) {
+        fbcon.cy = fbcon.rows - 1;
+        scroll_up();
+    }
+}
+
+static void put_char(uint8_t ch) {
+    switch (fbcon.esc) {
+    case ESC_START:
+        fbcon.esc = ch == '[' ? ESC_CSI : ESC_NONE;
+        if (ch == 'c')
+            clear_screen();
+        return;
+    case ESC_CSI:
+        if (ch >= 0x40 && ch <= 0x7e)
+            fbcon.esc = ESC_NONE;
+        return;
+    case ESC_NONE:
+        break;
+    }
+
+    switch (ch) {
+    case 0x1b:
+        fbcon.esc = ESC_START;
+        break;
+    case '\n':
+        newline();
+        break;
+    case '\r':
+        fbcon.cx = 0;
+        break;
+    case '\b':
+        if (fbcon.cx > 0)
+            fbcon.cx--;
+        break;
+    case '\t':
+        fbcon.cx = (fbcon.cx + 8) & ~(size_t)7;
+        if (fbcon.cx >= fbcon.cols)
+            newline();
+        break;
+    default:
+        if (fbcon.cx >= fbcon.cols)
+            newline();
+        draw_glyph(fbcon.cx++, fbcon.cy, ch);
+        break;
+    }
+}
+
+static void fbcon_write(struct console* con, const char* buf, size_t count) {
+    for (size_t i = 0; i < count; i++)
+        put_char((uint8_t)buf[i]);
+}
+
+static bool fbcon_setup(struct console* con) {
+    const struct boot_framebuffer* fb = &fbcon.fb;
+    if (fb->bytes_per_pixel != 4 || fb->red.size > 8 || fb->green.size > 8 || fb->blue.size > 8)
+        return false;
+
+    fbcon.fg = pack_color(FG_COLOR);
+    fbcon.bg = pack_color(BG_COLOR);
+    fbcon.cols = fb->width / FONT_WIDTH;
+    fbcon.rows = fb->height / FONT_HEIGHT;
+    fbcon.offset_x = (fb->width % FONT_WIDTH) / 2;
+    fbcon.offset_y = (fb->height % FONT_HEIGHT) / 2;
+    if (!fbcon.cols || !fbcon.rows)
+        return false;
+
+    clear_screen();
+    return true;
+}
+
+static struct console fbcon_con = {
+    .name = "fbcon",
+    .init = fbcon_setup,
+    .write = fbcon_write,
+};
+
+[[__init]]
+void fbcon_init(struct boot_info* info) {
+    const struct boot_framebuffer* fb = &info->fb;
+    if (!fb->base)
+        return;
+
+    fbcon.fb = *fb;
+
+    const size_t pgsz = arch_mem_page_size();
+    const phys_t start = ALIGN_DOWN(fb->base, pgsz);
+    const phys_t end = ALIGN_UP(fb->base + fb->pitch * fb->height, pgsz);
+
+    for (phys_t p = start; p < end; p += pgsz) {
+        errno_t status =
+            pmap_map(&kernel_vma.pmap, (uintptr_t)HHDM_PTR(p), p, PTE_READ | PTE_WRITE, CACHE_WRITE_COMBINE);
+        if (status)
+            return;
+    }
+
+    fbcon.back = mem_alloc(fb->width * fb->height * sizeof(uint32_t), ALLOC_NOZERO);
+    if (!fbcon.back)
+        return;
+
+    console_register(&fbcon_con);
+}
+INIT_TASK(fbcon_stage, "core.fbcon", fbcon_init);
+INIT_DEPENDS(fbcon_stage, sched_stage);

dev/video/fbcon/meson.build

@@ -0,0 +1 @@
+kernel_sources += files('fbcon.c')

dev/video/meson.build

@@ -0,0 +1,3 @@
+if kconfig.get('CONFIG_FBCON', 'n') == 'y'
+    subdir('fbcon')
+endif

fs/exec/elf.c

@@ -1,56 +1,92 @@
-#include <zinnia/mem.h>
-#include <zinnia/status.h>
-#include <common/elf.h>
-#include <common/utils.h>
-#include <kernel/alloc.h>
-#include <kernel/arch.h>
-#include <kernel/elf.h>
-#include <kernel/percpu.h>
-#include <kernel/pmap.h>
-#include <kernel/print.h>
-#include <kernel/sched.h>
-#include <kernel/vas.h>
-#include <kernel/vdso.h>
-#include <kernel/vmo.h>
-#include <assert.h>
-#include <string.h>
+#include <zinnia/alloc.h>
+#include <zinnia/assert.h>
+#include <zinnia/elf.h>
+#include <zinnia/errno.h>
+#include <zinnia/mman.h>
+#include <zinnia/percpu.h>
+#include <zinnia/pmap.h>
+#include <zinnia/print.h>
+#include <zinnia/sched.h>
+#include <zinnia/utils.h>
+#include <zinnia/vfs.h>
+#include <zinnia/vma.h>
+#include <zinnia/vmo.h>
+#include <bits/elf.h>
+#include <stdckdint.h>
 
-zn_status_t elf_load(struct exec_info* info, struct task** out) {
-    zn_status_t status;
+errno_t elf_load(struct exec_info* info, struct task** out) {
+    errno_t err;
 
     size_t read;
-    struct elf_ehdr ehdr = {};
-    vmo_read(info->file_obj, 0, &ehdr, sizeof(ehdr), &read);
+    elf_ehdr_t ehdr = {};
+    err = vmo_read(info->file_obj, 0, &ehdr, sizeof(ehdr), &read);
+    if (err)
+        return err;
+    if (read != sizeof(ehdr))
+        return ENOEXEC;
 
     // Check if the file is an ELF.
     if (memcmp(ehdr.e_ident, ELF_MAG, sizeof(ELF_MAG)) != 0)
-        return ZN_ERR_INVALID;
+        return EINVAL;
     if (ehdr.e_ident[EI_VERSION] != EV_CURRENT)
-        return ZN_ERR_INVALID;
+        return EINVAL;
     if (ehdr.e_ident[EI_CLASS] != ELF_ARCH_CLASS)
-        return ZN_ERR_INVALID;
+        return EINVAL;
     if (ehdr.e_ident[EI_DATA] != ELF_ARCH_DATA)
-        return ZN_ERR_INVALID;
+        return EINVAL;
     if (ehdr.e_machine != ELF_ARCH_MACHINE)
-        return ZN_ERR_INVALID;
+        return EINVAL;
     if (ehdr.e_type != ET_EXEC)
-        return ZN_ERR_INVALID;
+        return EINVAL;
+    if (!arch_mem_addr_is_user(ehdr.e_entry))
+        return ENOEXEC;
+
+    const size_t phdrs_size = (size_t)ehdr.e_phnum * ehdr.e_phentsize;
+    uintptr_t phdrs_end;
+    if (ehdr.e_phentsize < sizeof(elf_phdr_t) || ehdr.e_phnum == 0 || phdrs_size > 64 * 1024)
+        return ENOEXEC;
+    if (ckd_add(&phdrs_end, ehdr.e_phoff, phdrs_size))
+        return ENOEXEC;
 
     const size_t page_size = arch_mem_page_size();
+    uintptr_t phdr_addr = 0;
 
     for (size_t i = 0; i < ehdr.e_phnum; i++) {
-        struct elf_phdr phdr = {};
-        vmo_read(info->file_obj, (ehdr.e_phoff + (i * ehdr.e_phentsize)), &phdr, sizeof(phdr), &read);
-        if (phdr.p_type == PT_LOAD) {
-            enum zn_vm_flags prot = 0;
-            if (phdr.p_flags & PF_R)
-                prot |= ZN_VM_MAP_READ;
-            if (phdr.p_flags & PF_W)
-                prot |= ZN_VM_MAP_WRITE;
-            if (phdr.p_flags & PF_X)
-                prot |= ZN_VM_MAP_EXEC;
+        elf_phdr_t phdr = {};
+        err = vmo_read(info->file_obj, (ehdr.e_phoff + (i * ehdr.e_phentsize)), &phdr, sizeof(phdr), &read);
+        if (err)
+            return err;
+        if (read != sizeof(phdr))
+            return ENOEXEC;
 
-            assert(phdr.p_offset % phdr.p_align == phdr.p_vaddr % phdr.p_align, "");
+        if (phdr.p_type == PT_PHDR)
+            phdr_addr = phdr.p_vaddr;
+
+        if (phdr.p_type == PT_LOAD) {
+            if (phdr.p_memsz == 0)
+                continue;
+            if (phdr.p_filesz > phdr.p_memsz)
+                return ENOEXEC;
+
+            uintptr_t seg_end;
+            if (ckd_add(&seg_end, phdr.p_vaddr, phdr.p_memsz))
+                return ENOEXEC;
+            if (!arch_mem_addr_is_user(phdr.p_vaddr) || !arch_mem_addr_is_user(seg_end - 1))
+                return ENOEXEC;
+
+            if (phdr.p_align > 1 && phdr.p_offset % phdr.p_align != phdr.p_vaddr % phdr.p_align)
+                return ENOEXEC;
+
+            if (phdr_addr == 0 && ehdr.e_phoff >= phdr.p_offset && phdrs_end - phdr.p_offset <= phdr.p_filesz)
+                phdr_addr = phdr.p_vaddr + (ehdr.e_phoff - phdr.p_offset);
+
+            enum prot_flags prot = 0;
+            if (phdr.p_flags & PF_R)
+                prot |= PROT_READ;
+            if (phdr.p_flags & PF_W)
+                prot |= PROT_WRITE;
+            if (phdr.p_flags & PF_X)
+                prot |= PROT_EXEC;
 
             const uintptr_t misalign = phdr.p_vaddr & (page_size - 1);
             const uintptr_t map_address = phdr.p_vaddr - misalign;
@@ -59,18 +95,21 @@ zn_status_t elf_load(struct exec_info* info, struct task** out) {
 
             // Copy the file data into its own mapping.
             struct paged_vmo* phdr_obj;
-            status = vmo_new_phys(&phdr_obj);
-            if (status)
-                return status;
+            err = vmo_new_phys(&phdr_obj);
+            if (err)
+                return err;
 
-            status = vmo_copy(&phdr_obj->object, phdr.p_offset, info->file_obj, phdr.p_offset, phdr.p_filesz, nullptr);
-            if (status)
-                return status;
+            err = vmo_copy(&phdr_obj->object, phdr.p_offset, info->file_obj, phdr.p_offset, phdr.p_filesz, nullptr);
+            if (err) {
+                vmo_unref(&phdr_obj->object);
+                return err;
+            }
 
             // We map more than we copied so the rest is filled with zeroed pages.
-            status = vas_map_vmo(info->space, &phdr_obj->object, phdr.p_vaddr, phdr.p_memsz, prot, phdr.p_offset);
-            if (status)
-                return status;
+            err = vma_map(info->space, &phdr_obj->object, phdr.p_vaddr, phdr.p_memsz, prot, phdr.p_offset);
+            vmo_unref(&phdr_obj->object);
+            if (err)
+                return err;
         }
     }
 
@@ -80,9 +119,9 @@ zn_status_t elf_load(struct exec_info* info, struct task** out) {
 
     // Allocate stack.
     struct paged_vmo* stack;
-    status = vmo_new_phys(&stack);
-    if (status)
-        return status;
+    err = vmo_new_phys(&stack);
+    if (err)
+        return err;
 
     // Fill in stack info.
     uintptr_t stack_off = stack_size;
@@ -96,8 +135,21 @@ zn_status_t elf_load(struct exec_info* info, struct task** out) {
     for (const char** ptr = info->argv; *ptr != nullptr; ptr++) {
         num_argv++;
     }
+
+    size_t strings_size = 0;
+    for (size_t env = 0; env < num_envp; env++)
+        strings_size += strlen(info->envp[env]) + 1;
+    for (size_t arg = 0; arg < num_argv; arg++)
+        strings_size += strlen(info->argv[arg]) + 1;
+
     uintptr_t* envp_offsets = mem_alloc(num_envp * sizeof(uintptr_t), 0);
     uintptr_t* argv_offsets = mem_alloc(num_argv * sizeof(uintptr_t), 0);
+    if ((num_envp && !envp_offsets) || (num_argv && !argv_offsets)) {
+        mem_free(envp_offsets);
+        mem_free(argv_offsets);
+        vmo_unref(&stack->object);
+        return ENOMEM;
+    }
 
     for (size_t env = 0; env < num_envp; env++) {
         const char nul = 0;
@@ -132,14 +184,6 @@ zn_status_t elf_load(struct exec_info* info, struct task** out) {
         vmo_write(&stack->object, stack_off, &zero, sizeof(zero), nullptr);
     }
 
-    // Add the init handle to the process namespace.
-    zn_handle_t init_handle = ZN_HANDLE_INVALID;
-    if (info->init_handle) {
-        status = namespace_add_desc(info->ns, *info->init_handle, &init_handle);
-        if (status)
-            return status;
-    }
-
 #define WRITE_AUXV(auxv, value) \
     do { \
         stack_off -= sizeof(uintptr_t); \
@@ -156,23 +200,24 @@ zn_status_t elf_load(struct exec_info* info, struct task** out) {
     WRITE_AUXV(AT_PHNUM, ehdr.e_phnum);
     WRITE_AUXV(AT_PHENT, ehdr.e_phentsize);
     WRITE_AUXV(AT_ENTRY, ehdr.e_entry);
-    WRITE_AUXV(AT_INIT_HANDLE, init_handle);
+    if (phdr_addr)
+        WRITE_AUXV(AT_PHDR, phdr_addr);
 
     // envp pointers.
     stack_off -= sizeof(uintptr_t);
     const uintptr_t zero = 0;
     vmo_write(&stack->object, stack_off, &zero, sizeof(zero), nullptr);
-    for (size_t env = 0; env < num_envp; env++) {
+    for (size_t env = num_envp; env > 0; env--) {
         stack_off -= sizeof(uintptr_t);
-        vmo_write(&stack->object, stack_off, &envp_offsets[env], sizeof(envp_offsets[env]), nullptr);
+        vmo_write(&stack->object, stack_off, &envp_offsets[env - 1], sizeof(envp_offsets[env - 1]), nullptr);
     }
 
     // argv pointers.
     stack_off -= sizeof(uintptr_t);
     vmo_write(&stack->object, stack_off, &zero, sizeof(zero), nullptr);
-    for (size_t arg = 0; arg < num_argv; arg++) {
+    for (size_t arg = num_argv; arg > 0; arg--) {
         stack_off -= sizeof(uintptr_t);
-        vmo_write(&stack->object, stack_off, &argv_offsets[arg], sizeof(argv_offsets[arg]), nullptr);
+        vmo_write(&stack->object, stack_off, &argv_offsets[arg - 1], sizeof(argv_offsets[arg - 1]), nullptr);
     }
 
     mem_free(envp_offsets);
@@ -183,20 +228,25 @@ zn_status_t elf_load(struct exec_info* info, struct task** out) {
     uintptr_t argc = num_argv;
     vmo_write(&stack->object, stack_off, &argc, sizeof(argc), nullptr);
 
-    status = vas_map_vmo(info->space, &stack->object, stack_start, stack_size, ZN_VM_MAP_READ | ZN_VM_MAP_WRITE, 0);
-    if (status)
-        return status;
+    err = vma_map(info->space, &stack->object, stack_start, stack_size, PROT_READ | PROT_WRITE, 0);
+    vmo_unref(&stack->object);
+    if (err)
+        return err;
 
     struct task_start_info* start_info = mem_alloc(sizeof(struct task_start_info), 0);
+    if (!start_info)
+        return ENOMEM;
     start_info->ip = ehdr.e_entry;
     start_info->sp = highest - stack_size + stack_off;
     start_info->arg = 0;
 
     struct task* result;
-    status = task_create(info->argv[0], info->space, info->ns, sched_to_user, (uintptr_t)start_info, &result);
-    if (status)
-        return status;
+    err = task_create(info->argv[0], info->space, sched_to_user, (uintptr_t)start_info, &result);
+    if (err) {
+        mem_free(start_info);
+        return err;
+    }
 
     *out = result;
-    return ZN_OK;
+    return 0;
 }

fs/exec/meson.build

@@ -0,0 +1,3 @@
+kernel_sources += files(
+    'elf.c',
+)

fs/meson.build

@@ -0,0 +1 @@
+subdir('exec')

fs/vfs/ident.c

@@ -0,0 +1,17 @@
+#include <zinnia/ident.h>
+
+static const struct ident kernel_identity = {0};
+
+const struct ident* ident_kernel() {
+    return &kernel_identity;
+}
+
+bool ident_in_group(const struct ident* identity, gid_t gid, bool use_real) {
+    if (gid == (use_real ? identity->gid : identity->egid))
+        return true;
+    vec_foreach(&identity->groups, i) {
+        if (vec_elem_get(&identity->groups, i) == gid)
+            return true;
+    }
+    return false;
+}

fs/vfs/init.c

@@ -0,0 +1,3 @@
+#include <zinnia/vfs.h>
+
+void vfs_init() {}

fs/vfs/meson.build

@@ -0,0 +1,4 @@
+kernel_sources += files(
+    'ident.c',
+    'init.c',
+)

include/arch/archctl.h

@@ -0,0 +1,6 @@
+#pragma once
+
+#include <zinnia/errno.h>
+#include <stdint.h>
+
+struct syscall_ret arch_archctl(uintptr_t op, uintptr_t value);

include/arch/cpu.h

@@ -0,0 +1,3 @@
+#pragma once
+
+#include <bits/cpu.h>

include/arch/elf.h

@@ -0,0 +1,3 @@
+#pragma once
+
+// TODO: Ensure bits are defining values right.

include/arch/irq.h

@@ -0,0 +1,8 @@
+#pragma once
+
+#include <zinnia/irq.h>
+
+bool arch_irq_set_state(bool state);
+bool arch_irq_get_state();
+void arch_irq_wait();
+errno_t arch_irq_alloc_msi(struct msi_line** out);

include/arch/mem.h

@@ -0,0 +1,29 @@
+#pragma once
+
+#include <zinnia/compiler.h>
+#include <stddef.h>
+#include <stdint.h>
+
+[[__pure]]
+bool arch_mem_addr_is_user(uintptr_t addr);
+
+[[__pure]]
+size_t arch_mem_page_size();
+
+[[__pure]]
+size_t arch_mem_page_bits();
+
+[[__pure]]
+size_t arch_mem_level_bits();
+
+[[__pure]]
+size_t arch_mem_num_levels();
+
+[[__pure]]
+uintptr_t arch_mem_hhdm_addr();
+
+[[__pure]]
+uintptr_t arch_mem_pfndb_addr();
+
+[[__pure]]
+uintptr_t arch_mem_mapping_addr();

include/arch/percpu.h

@@ -0,0 +1,7 @@
+#pragma once
+
+#include <zinnia/percpu.h>
+
+struct percpu* arch_percpu_get();
+void arch_percpu_bsp_init();
+void arch_percpu_init();

include/arch/sched.h

@@ -0,0 +1,25 @@
+#pragma once
+
+#include <zinnia/errno.h>
+#include <zinnia/sched.h>
+
+struct percpu;
+
+void arch_sched_preempt_disable();
+bool arch_sched_preempt_enable();
+void arch_sched_kick(struct percpu* cpu);
+struct task* arch_sched_switch(struct task* from, struct task* to);
+errno_t arch_task_init(
+    struct arch_task_context* context,
+    void* entry,
+    uintptr_t arg0,
+    uintptr_t stack_start,
+    bool is_user
+);
+void arch_task_fini(struct arch_task_context* context);
+void arch_task_fork(struct arch_task_context* dst);
+void arch_context_init_user(struct arch_context* ctx, uintptr_t ip, uintptr_t sp);
+[[noreturn]]
+void arch_sched_jump_to_context(struct arch_context* context);
+[[noreturn]]
+void arch_sched_jump_to_user(uintptr_t ip, uintptr_t sp, uintptr_t arg);

include/arch/timer.h

@@ -0,0 +1,5 @@
+#pragma once
+
+#include <stdint.h>
+
+void arch_timer_program(uint64_t deadline_ns);

include/arch/usercopy.h

@@ -0,0 +1,10 @@
+#pragma once
+
+#include <zinnia/compiler.h>
+#include <zinnia/usercopy.h>
+#include <stddef.h>
+
+void arch_usercopy_allow(bool state);
+bool arch_usercopy_read(void* dst, const __user void* src, size_t len, struct usercopy_region** region);
+bool arch_usercopy_write(__user void* dst, const void* src, size_t len, struct usercopy_region** region);
+bool arch_usercopy_strlen(const __user char* str, size_t max, size_t* len, struct usercopy_region** region);

include/ipc/common.h

@@ -1,36 +0,0 @@
-#pragma once
-
-#include <zinnia/channel.h>
-#include <zinnia/handle.h>
-#include <common/utils.h>
-#include <stdint.h>
-
-#define ZN_IPC_NUM(group, num) ((uint32_t)(group) << 24u) | ((uint32_t)(num) & 0xffffffu)
-
-#define ZN_IPC(name, group, num, num_handles) \
-    name##_inner; \
-    constexpr uint32_t name##_num = ZN_IPC_NUM(group, num); \
-    typedef struct { \
-        uint32_t id; \
-        zn_handle_t handles[num_handles]; \
-        name##_inner inner; \
-    } name
-
-#define zn_ipc_write(channel, obj) \
-    zn_channel_write(channel, (obj)->handles, &(obj)->inner, ARRAY_SIZE((obj)->handles), sizeof((obj)->inner))
-
-#define zn_ipc_read(channel, obj) \
-    zn_channel_read( \
-        channel, \
-        (obj)->handles, \
-        &(obj)->inner, \
-        ARRAY_SIZE((obj)->handles), \
-        sizeof((obj)->inner), \
-        nullptr, \
-        nullptr \
-    )
-
-#define zn_ipc_new(name) \
-    (zn_ipc_fw_rsdp) { \
-        .id = name##_num \
-    }

include/stdarg.h

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: ISC
+#pragma once
+
+typedef __builtin_va_list va_list;
+
+#undef va_start
+#define va_start(v, ...) __builtin_va_start(v, 0)
+
+#undef va_end
+#define va_end(v) __builtin_va_end(v)
+
+#undef va_arg
+#define va_arg(v, l) __builtin_va_arg(v, l)
+
+#undef va_copy
+#define va_copy(d, s) __builtin_va_copy(d, s)