sse support

src/arch/x86_64/cpu.c

@@ -37,4 +37,15 @@ void cpu_state_init(){
 	// undefined opcode exception will handle system calls then
 	else printf("CPU%lu: syscall instruction not supported\n", arch_getcls()->lapicid);
 
+	// enable SSE	
+	
+	asm volatile(	
+		"mov %%cr0, %%rax;"
+		"and $0xFFFB, %%ax;"
+		"or  $2, %%eax;"
+		"mov %%rax, %%cr0;"
+		"mov %%cr4, %%rax;"
+		"or  $0b11000000000, %%rax;"
+		"mov %%rax, %%cr4;"
+		: : : "rax");
 }

src/arch/x86_64/include/arch/regs.h

@@ -6,6 +6,7 @@
 
 typedef struct{
 	uint64_t gsbase, fsbase;
+	uint8_t  fx[512];
 } arch_extraregs;
 
 typedef struct{

src/arch/x86_64/regs.c

@@ -4,13 +4,16 @@
 void arch_regs_saveextra(arch_extraregs* regs){
 	// user gs was swapped
 	regs->gsbase = rdmsr(MSR_KERNELGSBASE);
-	regs->fsbase = rdmsr(MSR_FSBASE);
+	regs->fsbase = rdmsr(MSR_FSBASE);	
+	asm("fxsave (%%rax)" : : "a"(&regs->fx[0]));
+
 }
 
 void arch_regs_setupextra(arch_extraregs* regs){
 	// gs will be swapped later
 	wrmsr(MSR_KERNELGSBASE, regs->gsbase);
 	wrmsr(MSR_FSBASE, regs->fsbase);
+	asm("fxrstor (%%rax)" : : "a"(&regs->fx[0]));
 }
 
 void arch_regs_setupkernel(arch_regs* regs, void* ip, void* stack, bool interrupts){