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https://github.com/Mathewnd/Astral.git
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Matheus
111 lines
3.3 KiB
C
111 lines
3.3 KiB
C
#ifndef _PCI_H
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#define _PCI_H
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#define PCI_BAR_BASE 0x10
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// 2 byte fields
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#define PCI_CONFIG_VENDOR 0x0
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#define PCI_CONFIG_DEVICEID 0x2
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#define PCI_CONFIG_COMMAND 0x4
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#define PCI_COMMAND_IO 0x1
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#define PCI_COMMAND_MMIO 0x2
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#define PCI_COMMAND_BUSMASTER 0x4
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#define PCI_COMMAND_IRQDISABLE 0x400
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#define PCI_CONFIG_STATUS 0x6
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#define PCI_STATUS_HASCAP 0x10
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// 1 byte fields
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#define PCI_CONFIG_REVISION 0x8
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#define PCI_CONFIG_PROGIF 0x9
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#define PCI_PROGIF_STORAGE_SATA_AHCI 0x1
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#define PCI_PROGIF_USB_EHCI 0x20
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#define PCI_PROGIF_USB_XHCI 0x30
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#define PCI_CONFIG_SUBCLASS 0xa
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#define PCI_SUBCLASS_STORAGE_NVM 0x8
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#define PCI_SUBCLASS_STORAGE_SATA 0x6
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#define PCI_SUBCLASS_SERIAL_BUS_USB 0x3
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#define PCI_CONFIG_CLASS 0xb
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#define PCI_CLASS_STORAGE 0x1
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#define PCI_CLASS_SERIAL_BUS 0xc
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#define PCI_CONFIG_HEADERTYPE 0xe
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#define PCI_HEADERTYPE_MULTIFUNCTION_MASK 0x80
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#define PCI_HEADERTYPE_MASK 0x7f
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#define PCI_HEADERTYPE_STANDARD 0
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#define PCI_CONFIG_CAP 0x34
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#define PCI_CAP_MSI 0x5
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#define PCI_CAP_VENDORSPECIFIC 0x9
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#define PCI_CAP_MSIX 0x11
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typedef struct {
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bool exists;
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int offset;
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} pcicap_t;
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typedef struct {
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uintptr_t address;
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uintptr_t physical;
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size_t length;
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bool mmio;
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bool is64bits;
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bool prefetchable;
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} pcibar_t;
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typedef struct pcienum_t {
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struct pcienum_t *next;
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int bus;
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int device;
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int function;
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int type;
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int class;
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int subclass;
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int progif;
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int vendor;
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int deviceid;
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int revision;
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pcicap_t msi;
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pcicap_t msix;
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pcibar_t bar[6];
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union {
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struct {
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int bir;
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uintmax_t tableoffset;
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int pbir;
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uintmax_t pboffset;
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size_t entrycount;
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} msix;
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} irq;
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} pcienum_t;
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uint8_t pci_read8(int bus, int device, int function, uint32_t offset);
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uint16_t pci_read16(int bus, int device, int function, uint32_t offset);
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uint32_t pci_read32(int bus, int device, int function, uint32_t offset);
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void pci_write8(int bus, int device, int function, uint32_t offset, uint8_t v);
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void pci_write16(int bus, int device, int function, uint32_t offset, uint16_t v);
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void pci_write32(int bus, int device, int function, uint32_t offset, uint32_t value);
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pcienum_t *pci_getenum(int class, int subclass, int progif, int vendor, int deviceid, int revision, int n);
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int pci_getcapoffset(pcienum_t *e, int cap, int n);
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pcibar_t pci_getbar(pcienum_t *e, int bar);
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void *pci_mapbar(pcibar_t bar);
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void pci_setcommand(pcienum_t *e, int mask, int v);
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size_t pci_initmsix(pcienum_t *e);
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void pci_msixsetmask(pcienum_t *e, int v);
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void pci_msixadd(pcienum_t *e, int msixvec, int vec, int edgetrigger, int deassert);
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size_t pci_initmsi(pcienum_t *e, int requested);
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void pci_msisetbase(pcienum_t *e, int base, int edgetrigger, int deassert);
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void pci_msisetmask(pcienum_t *e, int vector, int value);
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void pci_init();
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#define PCI_READ32(e, offset) pci_read32(e->bus, e->device, e->function, offset)
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#define PCI_READ16(e, offset) pci_read16(e->bus, e->device, e->function, offset)
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#define PCI_READ8(e, offset) pci_read8(e->bus, e->device, e->function, offset)
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#define PCI_WRITE32(e, offset, value) pci_write32(e->bus, e->device, e->function, offset, value)
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#define PCI_WRITE16(e, offset, value) pci_write16(e->bus, e->device, e->function, offset, value)
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#define PCI_WRITE8(e, offset, value) pci_write8(e->bus, e->device, e->function, offset, value)
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#endif
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