riscv64: fix build

build.zig

@@ -225,7 +225,6 @@ fn addKernel(b: *std.Build, plat: config.Platform, optimize: std.builtin.Optimiz
         },
         .riscv64 => {
             kernel.root_module.addAssemblyFile(b.path("src/kern/riscv64/locore.s"));
-            kernel.root_module.addAssemblyFile(b.path("src/platform/riscv64/trap.s"));
         },
         else => {},
     }

src/kern/riscv64/impl.zig

@@ -1,6 +1,13 @@
 const r = @import("root");
 const ke = r.ke;
-const rv64 = r.arch;
+const rv64 = @import("arch");
+const std = @import("std");
+
+const int = @import("int.zig");
+
+comptime {
+    std.testing.refAllDecls(int);
+}
 
 pub const tlb_max_pages = 32;
 

src/kern/riscv64/int.zig

@@ -1,6 +1,7 @@
 const r = @import("root");
 const ke = r.ke;
 const std = @import("std");
+const rv64 = @import("arch");
 
 export fn riscv_trap_handler(cause: usize, pc: usize) callconv(.c) void {
     if (cause == ((@as(usize, 1) << 63) | 5)) {